Wafer-level packaging (WLP) is building a head of steam in the small chip sector. This switch to WLP is stoked by a clear cost-reduction imperative. Much of the initial buildup is outsourced to contract manufacturers, but production is likely to be brought in-house to reduce costs and simplify logistics as the freight gets rolling. Fundamental Change WLP chips shipped directly to system assemblers bypass the traditional offshore package assemblers. This paradigm shift presages a fundamental change in the existing packaging infrastructure. Today's division of labor was set out more than a quarter century ago when ICs were shipped offshore for packaging in countries with low-cost labor. Packaging was cast off as a mature, labor-intensive technology with no strategic value. Under-standably, semiconductor manufacturers concentrated on system architecture and wafer fab. Then BGA and CSPs changed everything as they surfaced in 1992. The assumptions anchoring the packaging industry were shaken by the advent of chip-scale packaging. The miniaturization of cell phones drove CSPs and micro-via substrates to unprecedented levels of growth. Suddenly, packaging became strategic, with inventive packaging concepts appearing monthly. More significantly, chip-size packaging enabled assembly of packages directly on the wafer. Wafer-level packages began to appear in 1996, only four years after the CSP revolution began. IC packaging was anything but mature. Initial Focus on Small Chips The initial production of WLP focused on small chips that were little more than flip chips dressed up for surface mounting. With no technological barriers, momentum built up rapidly in analog, power and RF applications using small chips. As it overflows into larger and more complex chips, WLP threatens to overturn some long-held assumptions. First, WLP is not labor intensive. Like its front-end cousins, WLP is driven by technology, cycle time and yield rather than labor costs. The rationale for offshore package assembly evaporates in the face of more important logistic, test and time-to-market considerations. Wafer-bumping houses are springing up in places around the world without regard to local labor costs. In the long term, wafer-level packaging is likely to be closely integrated into the fab.
Second, WLP goes beyond simple packaging in providing added chip functionality and performance. Wiring layers can be added for power, ground, clocking, testing and intrachip communication. With these features, the package is essential for chip functionality. Third, test and burn-in can be greatly simplified by integration into the backend processes. Because test consumes an ever-greater portion of production cost, many IC manufacturers are pursuing a strategy of integrating burn-in and test into a simplified process flow. Where is WLP headed? In markets where WLP provides compelling advantages, packaging is being pulled closer to the wafer fab. We envisage a scenario in which chips are finished in the fab and shipped directly to systems assemblers without benefit of conventional single-chip packaging assembly. The convergence of fab and assembly will be examined in the International Wafer-Level Packaging Conference, slated for August 22 in Sunnyvale. The program is sponsored by Chip Scale Review [chipscalereview. com], MEPTEC [mepteconline.com] and Micro-Electronics Forum [microelectronicsforum.com]. The key issues include: Who supplies the technology and the equipment? What is the role of merchant packagers? How will protocols and standards be set? And where is packaging headed?
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