July - August 1999 - ChipScale Review

July - August 1999


eMail the Editor

The Impact of PC Board Surface Finish on

SMT Assembly Process Yield and Reliability


By Vern Solberg
Contributing Editor

Achieving a flat, uniform attachment site will allow for greater control of the solder paste print uniformity, extremely important when attaching fine-pitch leadframe or BGA devices. Plating and/or coating options include alternative alloys and/or chemistry.

Plating process options in wide use include hot-air-leveled tin/lead (HASL), immersion gold over electroless nickel and electroplated gold over electroplated nickel. Coatings are generally identified as a chemical preservative to prevent oxidation on the surface of bare-copper attachment sites.

Because of the uneven surface condition of the tin/lead finish, many companies are specifying nickel/gold over the copper base. PC board fabricators will typically use the tin/lead-plated circuit pattern as an etch resist, but strip the tin/lead after etching. One of the more popular plating finishes is the gold over a nickel barrier.

In this plating process, following solder-mask application, the exposed attachment sites and holes on the boards are plated with an electroless nickel alloy followed by a thin (flash) coating of gold alloy using a liquid immersion process.

The electroless/immersion plating provides a uniform surface finish. Of all the coating and plating options noted, Ni/Au is the most versatile (as long as the gold thickness is within the range of 0.08 µm-0.23 µm in thickness and nickel plating does not exceed 2.5 µm-5.0 µm in thickness).

The advantage the plating processes offer over preservative coatings is shelf life and a permanent coverage over exposed copper on vias, or other features not exposed to a solder process. Gold over nickel, a dominant plating technology in Asia, will provide excellent solder attachment process control as long as the gold thickness is limited (electroplating Ni/Au process is not recommended).

On the other hand, coating over bare copper is the most economical method of achieving a flat, uniform attachment site for SMT. Although handling and storage are concerns that must be addressed, the organic preservative materials have a unique advantage over other coating options.

Recommended electroless
nickel thickness2 µm-5.0 µm (1.3 µm mimimum)


Recommended immersion
gold thickness0.08 µm-0.23 µm

Source: IPC-2221, General Standard on Printed Board Design

When there is a choice between HASL, Ni/Au and OSP finishes for mass reflow soldering of surface mount assemblies, OSP (when handled properly) has proven itself in meeting both cost objectives and improved overall assembly process yield.

Primary Issues

Assembly process yield and product reliability are the primary issues facing manufacturers of electronic products. Although electronics as a category encompasses a very wide spectrum of packaging technology, solder attachment and interconnecting of the devices with printed circuits continues to be the most practical and economical method of assembly.

Although device packaging, as a rule, has been developed to be compatible with most solder attachment technologies, many of the newer, high-performance CSP devices may require a more controlled process. The devices have a relatively close contact pitch, requiring a uniform and flat surface for attachment.

Because of the higher contact density of these component families, assembly specialists have found that both PC board quality and surface finish will directly affect the overall manufacturing process yield.

To ensure that the manufacturer can meet the criteria for efficient, cost-effective electronic products, the surface finish specified for the PC board must be compatible with all aspects of the assembly process.

The industry can no longer assume that a single finish specification for the board will be acceptable for all applications.

Contact Mr. Solberg at Tessera by e-mail, vern@tessera.com or by phone at 408.383.3614.



Chip Scale Review o 7291 Coronado Drive, Suite 8 o San Jose, CA 95129 o Email: editor@chipscalereview.com



Application Notes, 99/08/06, 99/08/09, ID=9907/departments1
Keywords=fs00 ae00

© 1998 ChipScale REVIEW