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Current Issue
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
August - September 2002
Industry News

TSMC's Variation on the FET Boasts Transistors 10x Smaller

By Terrence E. Thompson, Senior Editor

Hsin-Chu, Taiwan-Taiwan Semiconductor Manufacturing Co. (TSMC) has demonstrated a CMOS IC with transistors that are some 10x smaller than those in today's most advanced production chips.

The TSMC device employs a variation of a field-effect transistor, known as a FinFET, because in 3D it resembles a fish's backfin. TSMC also claims the new FinFET will set "performance records," but the company declined to offer specifics.

TSMC sources believe FinFET packaging and testing challenges will be much the same as they are today. Leakage will continue to be an issue, making the package hot, especially during accelerated testing or testing at high speed.

Operational Parts

The Taiwan-based company-now the world's largest wafer foundry-has produced operational FinFETs with gate lengths of 35 nm. Initial tests of the P- and N-type transistors comply with leakage targets set by industry roadmaps for transistors of this size, according to TSMC.

Researchers have simulated the FinFET structure to operate within generally acceptable parameters at gate lengths as small as 9 nm, according to Dr. Chenming Hu, TSMC's chief technical officer.

A FinFET overcomes gating difficulties by providing a second gate, allowing both sides of the source-and-drain structure to be closed at the same time. Double gating, says Dr. Hu, reduces leakage and allows for further shrinkage of the transistor size with increased current.

Traditional transistors involve two components. One provides source and drain routes for the electrical current; the other gates the current. Gating, which is similar to pressing a finger on a vein, creates the classic ones and zeroes. [tsmc.com]

ASAT, Hana, STATS Announce Management Changes

Harry Rozakis
Tan Lay Koon

Three major Asian-based packaging foundries, ASAT, Hana Microelec-tronics and STATS, recently announced changes in top management.

ASAT Holdings Ltd., Hong Kong, announced that Harry K. Rozakis, its recently appointed CEO, will also direct the company's sales and marketing efforts.

Rozakis, former co-owner of the MEPPE Group (now MEPTEC), was named ASAT Holding's CEO in May. He most recently served with EEMS Singapore, and earlier with ChipPAC, Reel Services Group and Tessera.

James T. Healy, president of ASAT Inc., Fremont, Calif., and senior vice president of worldwide sales and marketing for ASAT holdings, recently resigned.

Additionally, Chip Scale Review learned during SEMICON West that three ASAT Inc. vice presidents have departed the company. Exiting were Alan Calamoneri, vice president of worldwide test operations; Edward C. Combs, vice president of engineering and a 15-year ASAT veteran; and Mike Stokman, vice president of strategic sales.

Bruce Stromstad

An ASAT spokesperson confirmed that an undisclosed number of employees were also furloughed from several of ASAT's U.S. sales offices.

The Bangkok-based Hana Microelec-tronics Group appointed Bruce Stromstad president of Hana Microelectronics Inc., San Jose. He fills a slot left open by the retirement of Richard Brancato nearly 1H years ago.

Earlier, Stromstad was president of Alphatec U.S., a vice president at ChipPAC, and the vice president of offshore manufacturing for Cirrus Logic.

STATS, Singapore, meanwhile, disclosed that Harry Davoody, its president and CEO, has resigned "to pursue other interests in the U.S." Tan Lay Koon has been promoted from STATS' CFO to president and CEO. He reports to Tan Bock Seng, STATS' chairman.

Lay Koon joined STATS in May 2000 as CFO. Previously, he was an investment banker with Salomon Smith Barney.

He earned a bachelor of engineering degree from the University of Adelaide, Australia. He also holds an MBA from the Wharton School of the University of Pennsylvania. [asat.com] [hanaus.com] [stts.com]

APiA Sending WLP Technology to Shanghai-Based IC Fabricator

San Jose-The Advanced Packaging and Interconnect Alliance (APiA), a trade group, says it will work with ACE Semiconductor, Shanghai, China, to provide a 200 mm wafer-level CSP line.

Once installed, due in the fourth quarter of this year, ACE will boast the first fully functional 200 mm wafer-level CSP line in China.

APiA says it will use a share of the line's capacity for development and demonstrations in support of the group's initiative to provide advanced packaging to China.

"We believe this agreement gives the APiA a strong foothold into China's burgeoning advanced packaging industry," said Ellery Buchanan, APiA chairman. [apialliance.com]

 
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