PATENT NUMBER: 6,407,929 ASSIGNEE: Intel Corp. INVENTORS: Dean Aaron, Michael Walk et al. TITLE: Electronic Package Having Embedded Capacitors and Method of Fabrication thereof This patent describes a method for embedding chip capacitors in a package substrate or interposer. Background Device speeds are increasing, and decoupling capacitance is needed to minimize power supply variations and hot spots. To be effective, this capacitance must be located as close to the chip as possible and with minimum parasitics. Capacitors can be mounted adjacent to the chip or under the chip. While mounting capacitors under the chip may reduce the interconnection distance, it may also interfere with how the device is mounted to the next level assembly. Hot spots are another reason to add capacitors close to the chip. These hot spots are portions of microprocessors or other chips that suddenly turn on and require sufficient power to prevent the voltage from drooping. While it is possible to locate decoupling capacitors around the edges of the die, the edges are frequently too far away to be effective. With package and substrate size decreasing, there is also less room around the perimeter of the chip to mount capacitors. The Invention The solution proposed in this patent is to place the needed capacitors inside the substrate where they can be located to best advantage. In some cases, these locations can be directly under the hot spot; in others, the capacitors can be located some distance away.
In its simplest form, one or more capacitors are bonded to a suitable pattern on the surface of a substrate layer. The capacitors can be thin film dielectric capacitors on Si, ceramic chip capacitors or other types. In one variation, the bottom electrode is conductively bonded to the copper pattern on the substrate. This connection can be made to a solder ball or to a nearby via.
The layer containing the capacitors is then coated with dielectric applied as a liquid, film or other form. Vias are formed in this layer to expose the top electrodes of the capacitors. They can be formed by drilling, laser ablation, etching or other processes. Contact to these electrodes can be achieved by several methods, including depositing a suitable conductive layer or by plating copper. Additional layers can be added to the substrate as needed, and capacitors can also be located on more than one layer. Various types of capacitor constructions are described in the patent. In one form, both electrodes are formed on the top surface of the capacitor; in another variation, one electrode is on top and one is on the bottom. The thin film capacitors are typically fabricated on silicon wafers, and these can be backgrinded to reduce their thickness. Depending on how the dielectric layer is applied over the capacitors, it may be necessary to planarize the surface of the dielectric layer, which may be accomplished by lapping or pressing.
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