Current Issue The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging August - September 2002 Email the editor

Gene Selven Publisher

Terry Thompson, our senior editor, and I, recently attended a wafer-level packaging (WLP) seminar presented by Semitool in Whitefish, Montana, not far from the equipment company's Kalispell home base.

While the conference may have been out-of-the-way geographically, it brought together some of the top packaging minds from the U.S., Europe and Asia. I'll try to give you a snapshot of the trends and observations outlined by expert speakers at the three-day conference:

• Bumping technology employed for WLP is pitch-dependent.

• Materials are becoming more important for 300mm WLP.

• Area array packaging includes flip chip and BGA.

• WLP drivers are ASICs, microprocessors, chip sets, DSPs, fast SRAMs and RF devices.

• Drivers for wafer-level CSPs are integrated passive devices (IPDs), analog and RF parts.

L to R: Paul Siblerud, Semitool; Terry Thompson, CSR; and Tom Bergman, Matrix Integrated Systems, talk over seminar topics.

Speakers also pointed out that WLCSP will be a core technology for MEMS. In other wafer-level applications, IPDs can be added by thin film processes. On the System-in-Package (SiP) front, one of the newest, hottest areas in device packaging, WLCSP, flip chip and CSP comprise the SiPs' basic repertoire of technologies.

No surpise, of course-as one speaker pointed out-is that by next year, all Japanese electronics companies will offer lead-free products.

Conference speakers from Europe noted that currently the largest application opportunities there include "Smart Paper," "Smart Labels" and the decades-old "Smart Cards."

In his presentation, Dr. Darrel Frear observed that the only alloys that are suitable replacements for lead/tin solders are themselves tin-based.

More tidbits from Whitefish:

• In Japan, wafer thinning has reached as low as 50 microns.

• Boise, Idaho's Micron has announced a 256-pin DRAM in a wafer-level package.

Several messages came through loud and clear at Whitefish. Loudest of all, perhaps, was that wafer-level packaging will be the most important single enabler of this decade, as far as advanced packaging is concerned.

Another key point was that companies that are not involved and/or invested in promoting, supplying or employing wafer-level packaging right now are at risk of being left behind when the technology train leaves the station. How valuable was this conference? Well, let me just report that I didn't even slip out to go fishing!

[gselven@ChipScaleReview.com]