This month issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics September - October 2000 Email the editor

David Francis	Linda jardine
Contributing Editors

PATENT NUMBER:
6,075,710

ASSIGNEE:
Express Packaging Systems Inc.

INVENTORS:
Dr. John H. Lau

TITLE:
Low-Cost Surface Mount Compatible Land Grid Array (LGA) CSP for Packaging Solder-Bumped Flip-Chips

Today there are more than 50 different kinds of CSPs. While the number of approaches continues to grow, many tend to be too expensive, too complex or too difficult to use in high- volume manufacturing applications. The approach taken in this patent is an attempt to simplify the CSP manufacturing process.

While CSPs are chosen primarily to reduce package size, they can also provide additional features like redistribution. Redistribution, which is the fanning out (or in) of the interconnect pattern from the IC to the larger pitch pads on the PWB, can be required for both perimeter and area array type ICs.

Often, this fanning out requires the substrate to be many times larger than the chip to provide the required transition. While the size of the substrate can be reduced by adding multiple layers, this also increases the cost and the complexity.

Two prior art examples are given in this patent. One example is the Motorola SLICC package, which features a flip-chip device with high-temperature solder bumps that are attached to the substrate with eutectic solder. The eutectic solder is applied to the substrate by screen printing.

The next example is an LGA-substrate CSP. This design employs a ceramic substrate, and the IC uses gold stud bumps. The IC is connected to the substrate using an isotropic conductive adhesive. This approach is not as reliable as other methods, due to the CTE difference between the ceramic substrate and the PWB.

Simple Approach

The approach described in this patent is a very simple one, as shown in the illustration. Pads on a flip-chip device (wafer) are flip-chip bumped using eutectic solder. The wafer is then tested, diced and sorted.

The substrate is a double-sided FR-4/5 (or the equivalent) with traces on one side connected with through-vias to the land grid pad pattern on the bottom side.

Assembly is accomplished by applying flux to the top of the substrate, placing the bumped chip and reflowing. After reflow, the chip is underfilled and packaged for shipping.

The assembler screen prints 6 mil thick solder paste on the PWB, places the CSP and reflows the paste with standard process.

Simple, low-cost land grid array CSP

Other Features

The ICs for this type of package typically feature perimeter pads and are of relatively low leadcounts. With this type of chip, the traces are fanned into the center of the package and then connected with plated-through holes to the land grid pattern on the bottom surface. Because of the fan-in approach, the substrate can be made very close to the size of the chip.

The copper surfaces of the CSP substrate (A TAB substrate can also be used) are coated with a suitable organic coating, while the pads are not solder coated. The solder mask, applied to the LGA pad surface, can overhang the pads or may be patterned so that the openings are slightly larger than the pads.

The chip metallurgy features a Ti/Cu under-bump metalization followed by electroplated eutectic solder, which is reflowed to form solder bumps.

A more detailed description of the processing steps used in this approach can be found in the 1998 NEPCON West Conference Proceedings (pp. 883-908).