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With chip-scale packages being employed in growing numbers, the industry is developing a new class of CSPs, generally referred to as wafer-level packages (WLPs). Wafer-level packages are formed on uncut wafers using deposition methods to form the "substrate" layers of the package. Singulation is performed after the packaging process is complete. The end result is a device that is face-down, offering the performance of flip-chip. This method, however, offers more than just flip-chip performance. WLP enables redistribution of the I/O, as well as additional wiring layers, which can be used to reduce I/O for power, ground and clock signals. Cost reduction is another driver behind WLP. Performing packaging functions en masse should enable serious cost reduction.
Standards Lacking However, minimum package cost does not necessarily lead to minimum component or system cost. WLPs tend to have non-standard sizes and non-standard I/O footprints. Die shrinks often cause changes in WLP size and I/O footprint. Changes in package size and I/O footprint are not often well received in the general PWB assembly community. To meet these issues, WLPs must be part of tightly integrated supply chains with large volumes and product design cycles that are coordinated with die shrinks at the wafer fab. WLPs, therefore, are not for everyone. Additionally, in spite of processes that build some materials compliance into the package, the small solder balls that are often required on WLPs may need underfill for reliable PWB assembly. The need for underfill is especially true for handheld devices-expected to be a major market for WLPs-due to rigorous drop-test requirements. Under-fill is an unpopular and costly process. Fortunately, National Semiconductor, National Starch and Chemical Co., and Georgia Tech are taking the notion of WLP a step further to resolve the underfill issue. In a three-year study funded by the Advanced Technology Program (ATP), the companies mentioned have developed a method of applying underfill on an entire packaged wafer. This method of application eliminates the need for costly underfill dispensing after the IC is placed on the board.1 The precoated underfill has a built-in flux and will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously.2 The presence of the underfill has also reduced chipping during dicing, eliminating the need for additional testing beyond the wafer-level. A variety of WLP designs have been introduced in the last few years, as shown in the graphic. However, the forecast for WLPs is rather modest. From a start of 16 million units in 1999, WLPs will grow to about 1 billion units in 2003. While this is a very high growth rate, the 2003 quantity represents less than 1 percent of expected IC shipments. 1. L. Nguyen, H. Nguyen, C. Quentin and E. Warner, "Issues in Wafer-Level Flip-Chip Under-fills," Proc. NEPCON West, Anaheim, Calif., February 2000. 2. Q. Tong, B. Ma, E. Zhang, A. Savoca et al., "Recent Advances on a Wafer-Level Flip-Chip Packaging Process," Proc. ECTC, Las Vegas, Nevada, May 2000.
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