This month issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics September - October 2000 Email the editor

Dr. Tom Di Stefano Contributing Editor

When will wafer-level packaging enter the mainstream? According to a panel of experts at a SEMICON West Wafer-Level Forum, WLP is rapidly becoming a reality for low I/O chips.

Several manufacturers, including Analog Devices, Dallas Semiconductor, Intarsia and National Semiconductor, are now shipping SMT-ready parts in rapidly growing numbers. For others, WLP is "in the future," limited by reliability and by the availability of high-density substrates, wafer test and burn-in.

A panel at the Forum noted that WLP technologies have differentiated to fit major applications rather than converging into one monolithic technology. Early wafer-level packages are being used for op-amps, power conditioners, integrated passives and RF devices in applications like watches and cell phones, where reliability requirements are not severe.

Low I/O Domain Leads

WLP expansion is most obvious in the low I/O domain, where CTE mismatch is not nearly as important to reliability as it is for larger memory and processor chips. Flip-chips can be reliably attached to standard PWBs using surface mount tech-nology, without underfill in most cases.

Wafer-level packages for these low I/O applications are typically little more than flip-chips dressed up for surface mounting. Standard boards can be routed to wire these low I/O chips, even at a grid pitch of 0.5 mm, because the I/O contacts are only 1-2 layers deep.

The picture for the larger and more complex chips is not as simple. Although a plethora of technologies has been introduced, the infrastructure is not ready to support them.

Reliability is the primary issue facing large dice mounted on standard boards. Flip-chips larger than 3 mm on a side cannot be reliably SMT-mounted without underfill and other special design considerations.

Different Approaches

Differential thermal expansion between chip and PWB is simply too great for reliable operation. To address this problem, a bewildering assortment of flexible links is being tried to make reliable connections between chip and substrate. Going beyond high-lead C4, these approaches include posts, springs, stacked solder balls, flexible balls, hollow balls, plated polymer bumps, filled elastomers, and encapsulated beam leads, among others. Each process requires its own supply infrastructure-something that will take years to build.

The extension of WLP to high I/O processors and ASICS is limited by the wiring capacity of conventional PWBs. High-density interconnect technologies are rapidly emerging for the DSPs and other high-I/O CSPs employed in wireless applications.

The explosive growth of HDI substrates will enable high-I/O WLP applications as the costs and capabilities mature over the next several years.

Graphic Illustrates how the infrastructure impacts WLP.

Wafer-level burn-in and test are needed if we are to gain the full benefits of wafer-level packaging of high-value chips, such as memory and processors. Despite significant resources thrown at KGD in years past, cost-effective solutions remain elusive. Recent advances by Matsushita, Motorola and others provide hope, however.

Motorola is reported to use sacrificial wiring on the wafer to burn-in BIST-enabled CPU chips. Wafer level burn-in, however, is not expected to be ready for broadscale use for several years.

Often overlooked, standards are needed to build an industry. Beyond package outlines, standardized manufacturing protocols and equipment are necessary. The continuing proliferation of package types, however, does little to advance the adoption of standards.