Current Issue The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging October 2002 Email the editor

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By Tom Bergman, Matrix Integrated Systems, Richmond, Calif.

As wafer-level packaging grows in popularity, users are searching for appropriate technologies to add to their arsenal of cleaning tools. Today, one of the most popular is plasma cleaning, employed for organic contaminant removal and surface conditioning of Si3N4, BCB and metal.

Yield Gains

Using plasma can provide dramatic yield gains, according to researchers. For example, plasma cleaning BCB for 15 to 30 seconds can improve yields from 75 percent to 100 percent.1

Figure 1. This chart indicates the potential yield benefit of plasma cleaning. (Fraunhofer Institute)

(A chart prepared by the Fraunhofer Institute, Berlin, showing yield benefits of plasma cleaning on BCB is shown in Figure 1.) Still, plasma processing may cause concern even with no yield loss and no damage due to a lack of understanding of how plasmas work.

Additionally, processing damage, including altered film quality or inadequate plasma cleaning time, may be wrongly blamed on plasma-induced damage.

There is a lengthy history of sensitivity to plasma damage in wafer fabs, where plasma damage is a real concern. As a result of experience at the front end, several well-established techniques have been developed to characterize plasma chambers and processes.

These techniques are effective as plasma chamber design aids, diagnostic tools and for use in troubleshooting plasma processes. They are also useful as yield and production QA monitors. Two of the better known systems involve the use of SPIDER and CHARM-2 wafers.

SPIDER or CHARM Wafers?

The SPIDER wafer is a key component in plasma troubleshooting. The SEMATECH consortium developed the SPIDER (SEMATECH Plasma-Induced Damage Effect Revealer) wafer for baselining plasma chambers. These wafers employ simple metal antennae structures on the wafer surface to collect electrical plasma charges.

These charges are routed to transistors, and cause a measurable shift in threshold voltage or gate leakage current.

Figure 2. RIE parallel-plate type plasma chamber

The SPIDER wafer has been employed to characterize a reactive ion etch chamber design (Figure 2) commonly used by WLP foundries.2 This chamber uses parallel plate electrodes, and produces a threshold voltage shift profile as a function of pressure versus power.

The SPIDER wafer offers many advantages: It is easy to use, and the entire wafer surface features active elements enabling plasma uniformity to be determined and reconciled with yield data.

CHARM Wafers

CHARM-2 wafers (Figure 3) also measure all possible damage mechanisms in plasma processing.3 They employ EEPROM-based sensors to measure peak voltages, currents and integrated UV flux, providing a complete picture of plasma behavior.

The output produced by CHARM-2 wafers is complex, reporting positive/ negative potential maps, J-V plots and UV intensity maps.

Figure 3. A negative voltage potential map

Figure 4. A downstream microwave plasma chamber design

Results from one CHARM-2 wafer suggested that further investigation and correction to yield was needed. In an experiment, the positive charge flux was 100µa at 8.0 V. Although potentially troublesome, this was non-damaging on a 35� gate oxide-consistent with gate oxide Fowler-Nordheim data and the antenna ratios used, as well as the correlation to actual yield data.4

It is important to recognize that actual IC device damage is strongly related to gate oxide quality. Although knowing damage potential is valuable, actual yield may vary, depending on layout, device structures and other factors.

Using MW Downstream Plasma

Another production option is the micro-wave downstream chamber, shown in Figure 4, where the plasma source is kept remote (downstream) from the chamber. A corresponding CHARM-2 map is shown in Figure 5.

As more packaging applications emerge, plasma processing technology should continue to provide benefits to the IC packaging community, supporting growth and enabling high yields.

Figure 5. A positive voltage potential map for the downstream system shown in Figure 4

References

1. Private correspondence with Michael Töpper, IZM, Berlin, Germany.

2. K. Donoghue, J. Werking, D. McCormack, "Characterization of Matrix 1178 Stripper System for Electrical Device Damage Using Statistical Modeling and SPIDER Wafers", 2nd International Symposium on Plasma-Process Induced Damage, pp. 157-160, 1997.

3. CHARM-2 is a registered trademark of Wafer Charging Monitors Inc.

4. Ming-Yi Lee, et al., Plasma-Process Induced Damage Symposium, pp. 104-107, 1999.

Mr. Bergman is the marketing director for Matrix Integrated Systems. He has held a variety of sales and marketing positions, and previously served at JDS Uniphase and BOC Gases. [tbergman@gomatrix.com]