Current Issue The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging October 2002 Email the editor

Infomation on products or services covered in this article

By Deborah S. Patterson, Kulicke & Soffa Flip Chip Div., Phoenix, Arizona

Solder ball array packages, whether defined as a ball grid array (BGA), a chip-scale package (CSP) or a wafer-level package (WLP), all address the need to reduce silicon and PWB footprint.

Today, the assembly of solder ball array packaging for pitches greater than 0.65mm is well understood. The migration to 0.5mm pitch continues to gain prominence, too, because of the compatibility of these devices to SMT assembly practices.

Figure 1. According to Prismark Partners, solder ball array packaging will post an average CAGR of 33 percent for BGAs and 38 percent for CSPs through 2006.

A majority of 0.5mm pitch components are offered as WLPs, with integrated passive and active designs (IP/IPAD) representing the first high-volume applications, which were introduced into cellular handsets in late 1999.

Figure 2a shows a solder-ball array, while 2b illustrates the array with a polymer ring surrounding the solder balls, which roughly doubles solder joint life.

Although assembly of 0.5mm pitch arrays is not yet offered though all electronics manufacturing service (EMS) providers, there has been widespread, high-volume adoption of this pitch within an extremely short period of time.

Array Packaging Will Flourish

Prismark Partners reports that solder ball array packaging will continue to flourish with healthy average compound annual growth rates (CAGR) of 33 percent for BGAs and 38 percent for CSPs through 2006(1).

In addition, WLPs are estimated to grow at an accelerated 80 percent CAGR through 2005. Figure 1 shows array package trends by pitch. Most experts expect that reduced pitches will continue to emerge in support of increased miniaturization. Developments in wafer level burn-in and test will also accelerate the use of WLPs.

Today, a majority of WLPs employ between 4-60 I/Os. Pitch, device area and reliability requirements are driving this I/O range.

For 0.5mm pitch footprints, array size does not typically extend beyond a 6x6 array. This limitation is driven by Weibull life requirements, coupled with the desire for underfill-free assembly.

Within the portable electronics sector, a 0.3mm-0.35mm diameter solder ball contained within a 6x6 array with a 0.5mm pitch does not require underfill to pass reliability requirements for solder fatigue or for impact, vibration and bending. The only exceptions relate to board design or device position.

Supported Products

The classes of product supported by WLPs include integrated passive and active devices, analog devices (temperature sensors, regulators, operational and power amplifiers). Also supported are serial EEPROMs, high-speed memory, high frequency/RF devices, LCD drivers, logic, microcontrollers and power and battery management devices.

The decision to use a WLP will continue to be driven by cost and yield. These low I/O devices are less costly in a WLP format compared to chips that are wirebonded into conventional leaded packages.

To extend WLP technology to other types of ICs, either the reliability must be improved to support larger arrays or the pitch must migrate below 0.5mm.

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