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Current Issue
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
October 2002

QFN Package Variation Improves on Thermal Specs
David Francis and Linda Jardine
Contributing Editors

PATENT NUMBER: 6,414,385

ASSIGNEE: Siliconware Precision Industries Co. Ltd.

INVENTORS: Chien-Ping Huang and Eric Ko

TITLE: Quad Flat Non-Lead Package For Semiconductor

In the original patent awarded to Matsushita in 1999, the QFN used a die pad that was completely inside the package. The die pad was offset somewhat from the perimeter leads and was slightly smaller than the die.

The die was mounted on the die pad and wire bonded to the perimeter leads, like most packages, and the only exposed pads were the perimeter leads.

While this design functions well, its thermal properties could be improved. Another limitation was that as the package was reduced in size, wire bonds were occasionally exposed, lowering the manufacturing yield.

This patent introduces a number of interesting variations to the basic bottom-leaded package design.

This graphic illustrates the patent's variations.

The Invention

In its simplest form, this patent employs the same approach as the original Matsushita patent, but it increases the offset of the die pad from the perimeter leads, enabling the die to be attached with the active face to the die pad.

A suitable thermal adhesive is used to bond the die to the pad (which is smaller than the die to minimize stress from TCE mismatch). The die pad is offset sufficiently far so that the top surface is flush with the top surface of the mold resin. Since the active surface of the die sits against this pad, its thermal properties are improved.

In a further effort to improve thermal performance, the thickness of the package can be reduced. The back surface of the die is exposed on the bottom of the package. All the variations require the perimeter pads to be located a sufficient distance from the die, contingent on the die size employed.

The next variation is a compromise between the two prior versions. Instead of exposing the backside of the die, a metal die pad (which does not appear to be part of the leadframe) can be bonded to the back side of the die so that it-rather than the die-is exposed after molding.

This patent introduces a number of interesting variations to the basic bottom-leaded package design.

The accompanying figure incorporates all of the variations described in this patent. The top die is bonded with its active surface to the die pad of the leadframe, and the die pad features a stepped surface to improve adhesion The die is attached with a thermally conductive adhesive.

The second die is adhesively bonded to the back surface of the top die.

A thermal pad is bonded to the front surface of the second die. This pad is exposed on the bottom of the package and can be soldered to a corresponding pad on a PWB. Both die pads are smaller than the die to minimize TCE problems and to avoid interfering with the bond pads.

The top die is wire bonded to the tops of the perimeter leads while the bottom die is bonded to the step in the bottom surface of these same leads.

Summary

This patent describes a number of ways in which the basic QFN approach can be extended to make it a smaller, more versatile package with improved thermal performance.

International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact David Francis or Linda Jardine by e-mail at iii1@ix.netcom.com or by phone at 650.728.5270. [iii1.com]

 
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