As CSP Technology Matures, Applications and Volumes Increase

The market for chip-scale packages continues to evolve as the technology matures and moves into high-volume production. While cellular handsets, the largest initial application, have received a great deal of attention, the adoption of CSPs in other applications promises even higher production volumes.

The maturing of the CSP industry can be viewed in three phases, with different driving forces for each phase. Ultimately, the demand for CSPs will come from designers who want to reduce system-level cost. This contrasts dramatically with initial CSP-based designs that could afford a price-premium for the small size benefit.

The important package factors are mechanical protection, size and thickness, electrical performance, heat dissipation and cost-not necessarily in that order. In the first phase of CSP adoption, the most important factors have been the smallest possible footprint and thickness.

Cellular phones and digital camcorders dominate this phase. Consumers happily pay extra for smaller and lighter products, forcing manufacturers to pay the higher costs associated with initial CSP production. Portable products have created a significant demand for package development and provided fuel for the industry to develop an infrastructure of materials, equipment and service providers.

The second phase of CSP adoption is now beginning: packaging high-speed DRAMs for computer memory. Electrical performance is the key driver in this phase. Small size contributes to electrical performance by decreasing the signal path, but the size of the end product is not a major design issue. Direct Rambus DRAM chips are the first class of DRAMs to require a ball grid array footprint. The combination of ball pitch and ball count with chip size and package size produces a package that fits neatly within the accepted definition of chip-scale package. Synchronous DRAMs can also benefit from the use of array packages instead of TSOPs, due to the relatively large number (60 to 90) of I/O.

The assembly market for CSP-based DRAMs promises to be larger than the portable product market as these high-speed memories move from workstations and high-end PCs to the overall computer industry. The DRAM market is notoriously cost-competitive and industry will choose the lowest-cost CSP solution that meets electrical and reliability requirements.

The third phase of CSP adoption will be the convergence of traditional BGA packages with CSPs into the general class of fine-pitch BGA (FBGA) packages. The 1.27-mm-and 1.0-mm-pitch BGA packages will shrink to 0.8-mm pitch. For ball counts less than 300, these packages will be indistinguishable from today's FBGA chip-scale packages and will become common in electronics assembly.

Telecommunications and automotive applications will adopt these packages for cost reduction. By the time the third phase is reached, chip-scale packaging will be the low-cost solution (see figure). Several factors are contributing to lower cost, including new assembly techniques such as wafer-level packaging; more efficient materials use, including strip-level overmolding; and learning-curve manufacturing improvements consisting of more parts per strip and higher throughput.

CSPs will evolve from a small package with an initial price premium used in portable products to a small package with inherent cost advantages. When that happens, most electronic assembly applications will benefit from CSPs. Lower system-level costs will come from low-cost packages, smaller PC boards and higher surface mount yields.