TAB as Flip-Chip Alternative Enables Rugged Area-Array Package

- By David Francis and Linda Jardine
International Interconnection Intelligence, Montara, Calif.

Patent Number:
5,909,010
Assignee:
NEC Corporation
Inventor:
Tatsuo Inoue
Title:
Chip-Size Package

The increasing use of large-scale ICs in portable and handheld equipment is driving the growing demand for smaller packages. Meanwhile, the trend for complete systems-on-a-chip, is leading to larger chips that either require increasingly larger packages or demand substantially smaller packages.

A second driver for smaller packages is telephone exchange equipment, which tends to use large numbers of ICs in close proximity.

The CSP patent featured here describes the general construction details of a relatively simple package. It addresses the general concept and not specific issues.

The approach described in this patent uses TAB technology to provide an area-array-type package that is a more rugged version of a flip-chip device.

Figure 1. Simple TAB CSP

When TAB is used as the connection method, the typical fanout to a PWB can occupy a significant amount of board area. This connection method results in a much larger distance between ICs and increases the time for signals to pass between chips.

While flip chip can be used to place chips much closer together, the problems associated with flip-chip reliability, handling, underfill and repair-together with the higher cost of the interconnect-tend to make this choice less desirable than alternatives.

Figure 1 illustrates the basic parts of this CSP. The substrate is smaller than the IC and features perimeter pads on the surface facing the IC. Area-array pads with bumps are located on the bottom surface.

The substrate can be any suitable material. FR-4 or other copper laminate would make it easy to form copper bumps on the bottom of the substrate. The substrate can contain internal layers, but it uses through-hole technology to connect the perimeter pads on one surface to the area- array pads on the other. (Figure 2 illustrates the basic assembly process.)

Figure 2. Assembly Process

Instead of bonding the chip first, the initial connections are made to the pads of the substrate.

The TAB leads are then TC-bonded to the IC's pads. During this process, the substrate is offset from the IC to allow later encapsulation. As shown, it appears that the unsupported ends of the TAB leads need to be much longer than normally found in a typical TAB bonding appli-cation. This length must be sufficient to reach the pads on the IC and allow room for whatever type tool is used to make the bonds.

The lead must also extend beyond the edge of the chip in order to simplify the excising step. If the leads are not accurately aligned to the substrate pads, or if bonding to the substrate pads causes a lead to misalign or twist, this could reasonably be expected to impact the yield when the IC is attached. This yield loss could be minimized if all of the leads were optically checked for position before bonding.

It may also be possible to leave strips of polyimide between sections to keep the leads from being misaligned.

The substrate appears to have bumps formed on the bottom surface, which would (appear to) eliminate the need for further bumping and should permit assembly using conventional solder paste screening and reflow.