September - October 1999 - ChipScale Review

September - October 1999


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Making Direct Chip Attach Transparent to Surface Mount Technology

A research team, with members drawn from the academic and commercial sectors, has been formed to investigate the technical and commercial challenges involved in making direct chip attach transparent to surface mount technology.

- By Dr. Larry Crane, Loctite Corp; Dr. Daniel Gamota, Motorola Labs; Dr. R. Wayne Johnson, Auburn University; Paul Neathway, Jabil Circuit Advanced Engineering Center

Figure 1. Electronic product with DCA

The development of a revolutionary DCA technology that solves critical industry roadblocks is needed. Specifically required is a high-performance, fluxing, reworkable underfill and processes for direct application of the materials to the die at the wafer level.

A vertically integrated research team has been formed to address the technical and commercialization challenges for making direct chip attach transparent to surface mount technology.

The team won an Advanced Technology Program (ATP) award in the 1998 National Institute of Standards and Technology (NIST) Microelectronics Manufacturing Infrastructure Initiative. Members are from Loctite Corp., an adhesives supplier; Jabil Circuit, an electronics manufacturing service provider; Motorola; and Auburn University, a university with extensive experience in electronics assembly and packaging.

Background

DCA on laminate (flip-chip on board) is used by a few OEMs, which prefer it because of the advantages of reduced product size and weight, improved electrical performance and higher interconnection densities (Figure 1).

These enabling characteristics are critical for future high performance and for portable products; they are equally important in other market segments. Furthermore, as IC density and I/O count continue to increase, wire bonding will reach its limit in I/O count and area-array DCA will be required.

However, integration of DCA technology does not offer a transparent conversion of a typical SMT assembly line. During the past three years, several enhancements to the DCA process have aided in reducing the number of non-SMT equipment and processes required for DCA. However, limitations in the current technology have prevented the transparent conversion sought by many manufacturers.

Issues Identified

The National Electronics Manufacturing Initiative (NEMI) and other organizations within the DCA assembly community have identified several critical materials and manufacturing issues for DCA. The constraints identified have limited the acceptance of DCA by electronics manufacturing service providers and smaller OEMs.

Specific challenges focus on the need for high-performance reworkable underfills and the elimination of dedicated underfill dispense and curing equipment.

Once transparent DCA technology implementation into SMT lines becomes possible, DCA global consumption can be expected to expand exponentially as more assemblers switch to the technology that offers all the performance and size advantages of traditional DCA without the historically high technology risks and steep learning curve.

The development of a revolutionary technology to solve critical industry roadblocks is required. This technology will integrate many elements of current global DCA process-simplification research into one virtual and vertically integrated research program.

Specifically, a high-performance, fluxing, reworkable underfill material and processes for direct application of the materials to die at the wafer level must be developed for SMT transparency (Figure 2).

The coated wafer will be cut to form single components. The individual die will be placed on the PWB, standard using pick-and-place equipment, similar to other SMT parts, and reflowed with no additional processing steps required. The pre-applied material will provide the necessary fluxing activity during soldering and will serve as the underfill following curing during the reflow process.

This innovative process will eliminate the individual underfill application for each die and the curing step during assembly, decreasing cost and making DCA truly transparent to the electronics assembler. The reworkable nature of the new material system will allow in-plant rework of defective units as well as repair of field-returned products.

Process Benefits
Figure 2. Propoed DCA process flow with wafer-applied material.

The proposed process benefits relative to present DCA assembly are reduction in facility cost (based on line space), line savings in initial capital layout and a reduction in depreciated equipment costs for a total reduction in cost per item. These savings will provide a significant competitive advantage.

Successful development and implementation of the proposed process will result in the net creation of more jobs for individuals at fabs to coat wafers with the developed material. Head count on SMT lines will remain unchanged, as employees who are currently monitoring traditional underfill dispense will be reassigned to backend assembly and test to allow the assembly line to run at the increased pulse rate facilitated by the implementation of the new DCA process.

Current Efforts

The leading industrial suppliers of underfill materials are continuing along evolutionary paths to provide incremental improvements in performance and processing1,2.

These improvements include increased adhesion to a variety of surfaces (Si3N4, SiO2, polyimide, solder mask, etc.), faster flow rates, shorter cure times, and the ability to flow in smaller gaps (required, as finer pitch dictates smaller bumps).

In addition to material improvements, variable frequency microwave curing has been developed to decrease the underfill curing time. While progress along these evolutionary paths may decrease the assembly processing time, the additional steps and equipment will not be transparent to the SMT line (see the table on page 53).

One area of development is a reworkable underfill. With current underfill materials, rework is virtually impossible after curing of the underfill. If rework is required, the assembly must be tested prior to application and curing of the underfill. This adds an electrical test step and cost to the standard SMT assembly process.

Moreover, the solder joints are rather fragile without underfill, and board flexing during handling can lead to solder joint fractures. This is of particular concern for thin laminate substrates commonly found in portable electronics. Additionally, field failures with underfilled die are not generally repairable. A machining process has been developed to grind the die and a portion of the underfill off of the board. This leaves a planar surface of underfill with solder remaining at the bump positions3.

A new die is then placed on the site and reflow soldered. However, this is not a practical solution.

Loctite4, National Starch and Chemical5 and the Georgia Institute of Technology6 are each developing reworkable underfill materials. While these materials, when commercialized, will address the reworkability issue, they will not eliminate the non-SMT manufacturing steps in the current DCA process.

Fluxing Underfill

A second area of development is a fluxing underfill. These materials serve as both the solder flux and the underfill. The material is dispensed or stenciled onto the printed circuit board, and the die is then placed and reflowed.

Kester, Emerson & Cuming7, Motorola8, Aguila Technology9, Loctite and the Georgia Institute of Technology are working on fluxing materials. While fluxing materials change the process and may decrease dispensing time, dispensing and curing steps are still required.

All current approaches to improve DCA reliability by the use of conventional underfill materials address the processing at board-level assembly. The concept proposed here moves this processing back to the wafer level. Wafer-level processing allows the underfill materials to be applied to hundreds of die at once, prior to or after the wafer has been bumped. This is much more efficient and cost-effective than individual application at the board level.

The concept of wafer-level processing of DCA has been introduced at several recent conferences10-16:

Development Goal

The goal proposed by the research team is to provide the critical revolutionary microelectronic materials, processing, and assembly technologies which will address and subsequently eliminate the critical issues identified by the National Electronics Manufacturing Initiative (NEMI) and other organizations.

The proposed device structure, which has a high-performance, fluxing, reworkable material applied directly to the die at the wafer level is shown in Figure 3.

Although the figure shows that solder is located only on the die, studies will be conducted to determine whether solder paste deposition on the PWB solder pads is required to form optimal solder joints.

Application of the fluxing and reworkable material, at the wafer/bump fab stage of the process, allows for a cost-effective application to hundreds, perhaps thousands, of dice at once.

Advanced Process
Figure 3. Propoed technology: Cross-section shows die with wafer-applied fluxing and reworkable material prior to placement.

The material, composed of thermoplastic or thermoset polymeric entities having chemical moieties with fluxing and reworkable attributes, will be applied to the wafer using an advanced process which is presently being developed. This pre-application approach creates a single component, similar to any other SMT part.

The coated die will be placed on the PWB using standard pick-and-place equipment and reflowed. No additional processing steps will be required. The pre-applied material will provide the necessary fluxing activity during soldering and will serve as the underfill by adhering (tack) to the laminate substrate while curing during the reflow process.

Technical Challenges

To allow the transparent insertion of DCA technology into conventional SMT assembly lines, a number of technical challenges must be addressed by this research team. A few of these challenges:

  • 1. Synthesis of a reworkable fluxing polymeric material (thermoset or themoplastic) which can be easily diced
  • 2. Development of processes and equipment for application of the material to a wafer
  • 3. Bumping the wafer either before material application or after
  • 4. Singulation of the dice from the wafer after material application
  • 5. Alignment of die with partially or no exposed solder balls for vision system pattern recognition and determination of the required placement accuracy for optimal joint formation (e.g. commercially available SMT equipment compatible)
  • 6. Development a model of the die structure and PWB which integrates the surface planarity effects and the complex surface energy forces of the materials and solder during placement and reflow (Figure 4)

While specific approaches, concepts and general strategies for the development of the material and processes have been developed, due to the proprietary nature of this technology the information cannot be disclosed until intellectual property has been secured.

Technology Demonstration
Figure 2. Modeling and experimental studies of the phenomena during placement of die. A: During placement regime. B: After placement regime.

The success of this program will be measured if the technology demonstrates no limitation for die size and pitch, provides enhanced reliability DCA and requires simple and manufacturable assembly and rework processes.

Die pitch-The proposed technology must not be limited by die pitch. Since the materials are applied directly to the wafer, the commonly observed DCA failures will not occur-solder extrusion into voids in the underfill which are adjacent to solder joints. Die size-During present DCA assembly, manufacturing is compromised when large die are used, due to the time required to encapsulate the solder joints; the encapsulation time to underfill the die is proportional to the die length squared. The time for encapsulation of the solder joints is immediate and should not be affected by die size.

However, one potential issue concerning die size for the proposed technology may concern the planarity of the applied material to the wafer. Recent studies, however, suggest that the planarity of the material on the wafer will be compensated when the solder joints collapse and wet the PWB bond pads during reflow.

Reliability-The proposed technology may offer JEDEC level 1 classification for flip-chip plastic ball grid arrays (FC-PBGAs) and CSPs. The application of the material directly to the wafer will enable the use of intrinsically higher viscosity materials, which typically have lower water absorption, reduced free volume and higher strengths of adhesion.

The proposed technology will have the potential to meet harsh reliability requirements: liquid-to-liquid thermal shock (1000 cycles from -65žC to 150žC), air-to-air temperature cycling (2500 cycles from -65žC to 150žC), and elevated temperature/high humidity testing (1000 hours @ 85%RH/85žC). This level of reliability will enable widespread industry acceptance of the technology developed.

Removal-Acceptable reworkable field-materials, equipment and processes do not exist, which limits the integration of DCA in electronic products. This program intends to develop the enabling rework technologies required for widespread integration of DCA into electronic products.

Acknowledgements

The authors thank Dr. Michael Schen, program manager, Electronics and Photonics Technology Office, Advanced Technology Program, NIST for his technical contributions and guidance. This effort is being partially funded under an award from the Advanced Technology Program, National Institute of Standards and Technology.

References
  • 1. M. Edwards, "Overview of Recent Advances in Flip-Chip Underfills," 4th International Symposium and Exhibition on Materials: Processes, Properties and Interfaces, March 15-18, 1998, Braselton, Ga.
  • 2. M. Shi, "Advances in DCA Underfill Material Cure Rates and Reliability," 4th International Symposium and Exhibition on Materials: Processes, Properties and Interfaces.
  • 3. Y. Tsukada, Y. Mashimoto and N. Watanuki, "A Novel Chip Replacement Method for Encapsulated Flip-Chip Bonding," Proc. 43rd Electronic Component and Technology Conference 1993, Orlando, Fla., pp. 199-204.
  • 4. L. Crane, A. Torres-Filho, et al., "Development of Reworkable Underfills, Materials, Reliability, and Processing," IEEE Transactions on Components and Packaging Technology, Vol. 22, No. 2, June 1999.
  • 5. Q. Ma, A. Tong, et al., "Novel Fast Cure and Reworkable Underfill Materials," 4th International Symposium and Exhibition on Materials: Processes, Properties and Interfaces.
  • 6. C. P. Wong, L. Wang, et al., "Novel No Flow and Reworkable Underfills for Flip-Chip Applications," 2nd International Advanced Technology Workshop on Low Cost DCA Technology, March 13-15, 1998.
  • 7. T. DeBarros, P. Neathway, and Q. Chu, "The No-Flow, Fluxing Underfill Adhesive for Low Cost, High Reliability Flip Chip Assembly," Proc. 49th Electronic Components and Technology Conference, June 1999.
  • 8. D. R. Gamota and C. M. Melton, "The Development of Reflowable Materials Systems to Integrate the Reflow and Underfill Dispensing Processes for DCA/FCOB Assembly," IEEE Transactions on Components, Packaging, and Manufacturing Technology Part C: Manufacturing, Vol. 20, No. 3, July 1997, pp. 183-187.
  • 9. A. Capote, S. Zhu, et al., "Reflow-Curable Polymer Fluxes for Flip-Chip Underfill Encapsulant," 4th International Symposium and Exhibition on Materials: Processes, Properties and Interfaces.
  • 10. A. Capote, "Simplified Flip-Chip Manufacturing: Multilayer DCA Encapsulants," International Advanced Technology Workshop on Flip-Chip Technology, March 15-18, 1998.
  • 11. L. Nguyen, "Rationale for Wafer Level Flip Chip Underfilling," International Advanced Technology Workshop on Flip-Chip Technology, March 1999.
  • 12. C. D. Johnson and D. F. Baldwin, "Wafer Scale Packaging Based on Underfill Applied at the Wafer Level for Low Cost Flip Chip Processing," International Advanced Technology Workshop on Flip-Chip Technology, March 1999.
  • 13. L. Crane, "Wafer Applied Underfill: Material Requirements," International Advanced Technology Workshop on Flip-Chip Technology, March 1999.
  • 14. M. Witty and A. Capote, "Flip Scale Packaging: Advances in Pre-encapsulated Flip Chip Technology," International Advanced Technology Workshop on Flip-Chip Technology, March 1999.
  • 15. P. Garrou, "Wafer Level Chip Scale Packaging," International Advanced Technology Workshop on Flip-Chip Technology, March 1999.
  • 16. S. H. Shi, T. Yamashita, et al., "Development of the Wafer Level Compressive Flow Underfill Process and Its Required Materials," Proc. 49th Electronic Components and Technology Conference.
Dr. Crane manages the Electronics Product Development Group at Loctite Corp., Rocky Hill. He earned degrees from the University of California, Riverside, in biochemistry and a Ph.D. from the University of California, Berkeley, in organic synthesis. Contact him at larry_crane@loctit.com or at 860.571.5497.

Dr. Gamota is a managerial leader at Motorola Labs. He leads a team that develops and implements materials and processes for manufacturing advanced electronics packages and products. He holds degrees in chemical engineering and a Ph. D. in materials science and engineering from the University of Michigan. Contact him at daniel.gamota@motorola.com or at 847.576.5084.

Dr. Johnson is an Alumni Professor of Electrical Engineering at Auburn University and director of the Laboratory for Electronics Assembly and Packaging (LEAP). His research focus is on advanced electronic assembly materials, processes and reliability. He received B.E. and M.Sc. degrees from Vanderbilt University and a Ph.D. from Auburn University, all in electrical engineering. Contact him at johnson@eng.auburn.edu or at 334.844.1880.

Mr. Neathway is a manager at the Jabil Circuit Advanced Engineering Center. He manages a group which is responsible for the selection and analysis of materials and equipment for DCA. He earned technical degrees in electronics from Algonquin College, Ontario, Canada and the Tampa Technical Institute, Florida. Contact him at paul_neathway@jabil.com or at 408.361.3200.



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