Wafer bumping requires dedicated new inspection methods to ensure profitable yields as device I/O counts increase and bump pitches tighten. The qualification of bumped die and the maintenance of bumping processes also require optical inspection of every bump on every die on each wafer.

With the rapid growth of wafer bumping, such prop-erties as bump planarity, volume, shape and presence must be evaluated on the fly at production speeds and compared wafer-to- wafer and lot-to-lot. This evaluation enables the immediate identification of solder-mask irregularities, stencil defects and other process anomalies.

According to a 1999 Prismark report[1] more than 2.3 billion flip-chips will be produced annually by 2002. Of these, 16 percent will be processors or complex ASICs with more than 400 bumped I/O connections.

Microprocessors already in produc-tion contain thousands of chemically vapor deposited or electroplated bumps, resulting in more than half a million bumps per wafer.

As bump pitch decreases and complex devices are produced on 300-mm wafers, the total number of bumps per wafer will exceed one million. By the bumping stage, such expensive wafer products will have acquired nearly their entire value, and their worth will depend on how strictly the bumping process can be monitored and controlled.

Inspect All Bumps

Defective bumps must be identified before wafer probing. Bumps that are too large, small or altogether missing can pass through probing without incident and lead to device failure.

Such failures waste the time spent testing the defective die and the packaging expense. There is always the chance that an IC with a bad bump (one that could have been discovered at the wafer stage) will work through final test but fail in the user's system.

Wafer probing is no screen for killer bump defects. In fact, many common bump anomalies can destroy probe cards, which can cost more than $60,000 each. For example, malformed bumps can bridge power and ground contacts, as can extraneous bump material, causing excessive current draw through a probe card.

Notably, The 1999 International Technology Roadmap for Semiconductors[2] projects that chips will eventually draw 140 Amps each at 1.2 V. Optical inspection prior to probing will be necessary to prevent damage to neighboring die if imperfect solder bumps are probed at such high current.

Bent Probes

Bumps that are too tall or irregular can bend probes. Beyond the direct cost of a new probe card, a damaged card incurs substantial costs for tester downtime, as well as the labor required to replace it.

Figure 1. The Electroglas Quicksilver inspection system	Figure 2. Of the available display formats for presenting bump position data, this Y-offset contour map is a graphical plot produced by the workstation, which highlights bumps that drifted from their ideal position. An X-offset map would be similiar.

Manual inspection of wafers to identify defective bumps is tedious, slow and prone to error, making it inefficient for production volume, especially the production of complex circuits that incorporate tightly packed bumps.

Automated inspection and defect classification is imperative to isolate bad die and quickly determine the cause of bump defects. A system for automated inspection must find abnormal bumps, plot their location and measure them, determine whether they are defective, categorize the abnormality and create a wafer map of bump defects. The system must also isolate bad die so that they will be skipped during probing and archive the data for continual process analyses.

Defect classification must include bridged bumps, missing bumps, too small bumps, excessive bump volume, too-short/too-tall bumps, bumps with nodules extending from them, misplaced bumps, bumps with satellite material between them and contaminated bumps.

Metrology tools used in the character-ization of front-end wafer processes certainly could provide extremely accurate measurements of bump profiles. However, they cannot inspect all the bumps on wafers at a production rate. Without 100 percent optical inspection, critical process flaws go unnoticed.

Defect Causes

Determining the exact causes of bump defects requires a very large database for archiving measurements and images, as well as tractable programs for correlating, analyzing and presenting the informa-tion. Certain repetitive bump defects recur only infrequently among wafers and may be construed as random anomalies if they are not linked to distant incidents.

Consider the molybdenum masks used in the C4 evaporative process. These masks are cleaned, examined and placed in inventory for reuse following bump deposition. At any time, a line may have dozens of the masks in service.

The consumable masks contribute the largest portion of the cost-per-wafer of the C4 process, which in total can add $270 to the cost of a 150-mm wafer. The longer a mask is used, the lower the wafer cost.

The mask inspection tools in common use are very good, but culling a defective mask depends upon an operator's atten-tion and skill, and some mask flaws are nearly indiscernible to the most trained eye. Moreover, a mask that is residue-free after cleaning may become contaminated before reuse.

Tracing bump defects to the mask that caused them can be very difficult because of the intervals between mask use. A CVD chamber usually holds less

than a typical lot of 25 wafers, making the correspondence between a particular mask and particular wafers over time complicated to establish without a very good system for data collection, analyses and management.

An automated optical bump inspection system (Figure 1) and related data-analysis tools are currently in use by manufacturers of advanced microprocessors. They have helped to quickly isolate random defects and the origins of chronic bump defects, which in some cases are endemic to bumping processes in widespread use.

This inspection system employs struc-tured lighting, along with a time delay and integration camera similar to those used in front-end metrology instruments, to reveal slight deviations from the contour and reflectivity of an idealized bump.

Training Period

After a short training period to tune the system for a particular product, bump dimensions are measured with an accu-racy nearly that of precision engineering metrology tools, but at a throughput of 30 wafers per hour with 100 percent bump inspection, regardless of wafer size, number of bumps or bump pitch. While the inspection system identifies defective bumps and forwards wafer maps (with bad die flagged) to operations downstream, a related workstation enables detailed analyses of the bump data supplied by one or more of the inspection systems.

Figure 3. Note the defect locations running along the straight line and intersecting several die areas (upper quadrant left).

For bump management using statistical process control, aggregate data and trends are more valuable than measurements of individual bumps.

For example, while the inspection system determines the volumes of individual bumps, the workstation calculates mean bump volume averaged over die, wafers or lots and presents the information to bump process engineers in the form of SPC charts and reports.

With the workstation, an engineer can visualize hundreds of megabytes of data from one or several of the inspection systems enabling strict control of bump processes. The system collects the measurements of defective bumps and archives the bump images for side-by-side review with those measurements, wafer maps and defect classifications. The dimensions of all bumps can be taken from repeated runs of the same wafer product over extended time to study process tool repeatability.

By archiving, tracking and analyzing bump data over many replicated wafers, the inspection tools have graphically shown a tendency of the C4 process to slightly displace bumps near the perimeter of wafers from their ideal locations.

Although that process of evaporative deposition generally results in highly uniform bump composition and volume, bump registration on die near the wafer edge must be closely monitored.

The cause of the slight misalignment is mask creep relative to the wafer (due to the differential in thermal expansion between the molybdenum mask and the silicon.) Displacements in bump location at the bump, die and wafer level can be presented in many different formats (Figure 2).

Figure 4a and 4b. Plots of mean bump height along perpendicular axes on a wafer ease identification of a sagging stencil.

Process-Specific Analyses

With respect to C4, the ability to archive and correlate defect data over distant, non-sequential wafers results in the identification of process problems that otherwise would be extremely difficult to isolate.

For example, bridged bumps were detected on several wafers. Among those wafers, the bumps bridged were not identical. However, by comparing and superimposing the locations of the defects, the inspection system revealed that the bridged bumps occurred in a straight line from wafer-to-wafer (Figure 3).

That analysis led to the discovery of a minute crack in a mask (between 2-3 cm long) which had been missed during mask inspection and was almost impossible to see.

With stenciled bumps, this inspection system identified variations of bump volumes across wafers in a consistent pattern among die. By automatically aggregating and converting bump height measurements along columns and rows of die into mean values, then displaying those column and row values as bar graphs, the pattern became immediately evident (Figures 4a & 4b).

The graph showed that bump mean height progressively increased from the wafers' centers outward. As a result of that display, the bump variation became easy to trace to sag in a stencil, which caused the openings at the stencil center to nearly close.

Another problem with a screen process was discovered by correlating a pattern of satellite material from wafer-to- wafer. The coincident wafer defects were traced to microscopic tears that were not evident during a routine inspection of the screen.

These tools also inspect, measure and analyze electroplated bumps, as well as C4 and printed bumps, with the same accuracy, after tuning for the properties of bumps that are ideal to the particular process.

Inspection After Wafer Probing

Finally, to insure the delivery of die with known good bumps at the wafer level, essential for wafer-level packaging techniques, bump inspection should occur again after wafer probing.

Probing can damage bumps, especially on wafers with. high bump counts, which require high vertical forces during testing to seat probes for proper contact. Mr. Kiest is vice president of engineering at Electroglas Inspection Products. He was co-founder of TechnŽ Systems, Oregon, and has developed numerous automated inspection systems for semiconductor and non-semiconductor manufacturing. [ckiest@electroglas.com]

References

1. Prismark Partners, Cold Springs Harbor, N.Y., 1999.
2. Semiconductor Industry Association, San Jose, Calif., 1999.