This month issue An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics November - December 2000 Email the editor

Mechanical cycling test results under different conditions are summarized and listed in Table 1. Conditions were failure under static deflection and failure under mechanical cycling with and without application of 4 V to the package/PWB daisy (chain resistance 3.2 Ohms).

The load deflection under static conditions was determined and found to have a linear relationship, i.e. as load increased, the deflection increased. The maximum deflection prior to failure was 5.65 mm (0.226 inch) under 4 volt condition. This value is expected to be higher if no current is applied to the daisy chain during testing.

To achieve accelerated failure to less than a day under 5 Hz cycling frequency (10,000 cycles for every 33 minutes), damage levels were accumulated under an increasing level of deflection. Deflection levels were increased when assemblies survived 10,000 cycles under one level of deflection.

Further acceleration was achieved by application of current to the daisy chain resistance of package/PWB. Data presented in Table 1 clearly indicates that assemblies failed under maximum combined deflection of 1.25 mm (.050 inch) for a 4 V condition. The maximum deflection increased to 1.875 mm (.075 inch) when no current was applied.

If no damage accumulation technique is used, then assemblies under deflection of .625 mm (0.025 inch), with and without current, failed at 104,000 and more than 400,000 cycles (300,000 cycles plus 87,000 at 0.050 inch), respectively. Note the MCTF reduction when assemblies were subjected to 150°C for only 20 minutes. This temperature and time represent cure of a reworkable underfill.

Figure 4. Cumulative failure distributions for several assembled fine pitch BGA packages, including two packages with 208 and 280 I/Os and three die sizes subject to 900 thermal cycles (-55/125°C)

Assemblies are currently being subjected to scanning electron microscopy, cross-sectioning and pull testing to determine failure mechanisms due to various accelerated mechanical cycling schemes.

Several observations, however, were made during mechanical cycling when assemblies start to show signs of failure. One aspect was included in Table 1 by listing the MCTF range from the start of daisy chain voltage/resistance increase to complete daisy chain open.

In general, an increase in resistance or voltage was slow, and sometimes it required thousands of additional cycles before a complete daisy chain open occurred under loading (deflection). Failure under load was not permanent for most cases, especially for a no-voltage condition. Daisy chains showed an increase in resistance after removal of load, but did not show a complete open. Under current application conditions, sometimes complete failure occurred under both load and no-load conditions.

New applications of advanced electronic packaging, including CSPs in consumer portable products, brought about new environmental requirements not seen in the previous generation of relatively benign office applications. The on/off cycles introduce failure of solder joints due to thermal mismatch of package and PWB. Solder joint integrity is critical since the joints carry both mechanical and electrical load.

Failure of solder joints due to CTE mismatch has commonly characterized the use of a dummy package daisy chained through solder joints and the PWB by monitoring their failure under temperature cycling. Use of power cycling, i.e. heating solder locally by imbedding resistance inside the package, is now being considered as an alternative since it provides higher reliability results which are badly needed for miniature packages.

In addition to on/off cycles, electronics in portable products are also required to be robust under mechanical conditions, i.e. robustness to repeated mechanical cycling due to key punching and to shock due to dropping or bending. The mechanical requirements are not new for high reliability application environments including automotive, military and aerospace.

Conventional leaded SMT packages have been shown to be robust. Unfortunately, both the use of rigid balls instead of flexible lead and a reduction of the interconnect area for most CSPs due to reduction in package size have negative effects on their environmental robustness.

Accelerated thermal and mechanical testing are required to screen for different designs and also to determine the robustness of CSPs to meet the increasing demand for time-to-market shrinkage for consumer products and effective use of these products for high reliability applications.

Mechanical cycling tests, if they provide the same trends as thermal cycling, could be a very effective acceleration technique. The investigation performed here was aimed at characterizing behavior of CSPs under mechanical cycling conditions and to determine if techniques can be developed to determine trends that are being established under thermal cycling conditions.

One key parameter that affects thermal cycles to failure is the CSP die size. Thermal cycling of packages with various die sizes clearly indicated the criticality of size and its effects on solder joint reliability. With limited tests performed, it appears that there is a possibility that such a trend can be established by mechanical cycling.

Mechanical tests with no local package heating will result in significantly overestimating the life of solder joints. Local heating will accelerate life testing and provide a better application representative.

Very promising accelerated test results under mechanical cycling were found for those assemblies exposed to isothermal aging at 150°C for 20 minutes. These assemblies clearly showed much lower mechanical cycles to failure, and the trend was apparent. Further work is required to determine if this accelerated technique could be used to screen for a variety of manufacturing defect and possibly, in conjunction with limited thermal testing, to project life for intended applications.

One key parameter that affects thermal cycles to failure is the CSP die size.

Conclusions

These conclusions are based on results limited to assembly failure to 900 thermal cycles in the range of -55°C to 125°C and a limited number of mechanical cycling tests to failure.

• Cycles-to-failures for the fine pitch ball grid array (FPBGA) with 0.8 mm pitch were in the range of 300 to 800 cycles. These are significantly lower than their BGA counterparts with 1.27 mm.
• Cycles-to-failure decreased as package die size decreased. The 208 I/O FPBGA package with the largest relative die size to package dimension (11.4 mm die in 15 mm package) showed the lowest cycles to failure, followed by the 280 I/O package with a slightly smaller relative die size to package (11.8 in 16 mm). The effects of die sizes were as follows:
• Eight out of eight of the 208 I/O assemblies with 11.4 mm die failed in the range of 176 to 573 cycles
• Fourteen out of 14 of the 280 I/O assemblies with 11.8 mm die failed in the range of 303 to 824 cycles
• Two out of 10 of the 280 I/O assemblies with 9.5 mm die failed at 690 and 836 cycles
• Three out of four of the 280 I/O assemblies with 7.3 mm failed at 824, 824 and 829 cycles
• The FPBGA failed at 5.7 mm maximum deflection under static bending load. It survived more than 400,000 mechanical cycles to maximum deflection of 0.625 mm (0.025"). This value decreased to about 100,000 cycles when packages were locally heated.
• The trend on the effects of die size, when sizes were far apart, could possibly be detected by the use of accelerated mechanical cycling and local heating of the package possibly due to heating and rigidity differences in loading. Accelerated mechanical testing detected the degradation effect of assemblies subjected to isothermal aging at 150°C for 20 minutes. Thus, such tests may be effective in screening for manufacturing defects, severe degradation due to environmental exposure and mechanical robustness for application.

The portion of research described here is being carried out by the Jet Propulsion Laboratory, California Institute of Technology, under a contract with NASA.

I wish to acknowledge the in-kind contributions and cooperative efforts of the JPL CSP Consortium. Special thanks to A. Arreola and T. Hills of JPL; M. Lam, D., Strudler and S. Umdekar of Hughes Network Systems and package suppliers and other team members who have made contributions to the progress of this program.

1. R. Ghaffarian, "Chip-Scale Packaging Guidelines," distributed by Interconnection Technology Research Institute, http://www.ITIR.org,
2. R. Ghaffarian, G. Nelson et al, "Thermal Cycling Test Results of CSP and RF Package Assemblies,", Proc. Surface Mount International, Chicago, Sept. 25-28, 2000.

Dr. Ghaffarian, a Chip Scale Review editorial advisor, is a widely known speaker and author on reliability in electronics. He currently supports R&D activities at the Jet Propulsion Lab, California Institute of Technology, Pasadena for BGAs, CSPs and surface mount technology. He received his Ph. D. in engineering from the University of California, Los Angeles. [reza.ghaffarian@jpl.nasa.gov]

Back