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 This month issue
An Independent Journal Dedicated to the Advancement of Chip - Scale Electronics

November - December 2000

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 Application-Driven Integrated Passives (SiP) Offers Low Die Cost

By Steve Berry and Sandra Winkler
Contributing Editors

The drive for higher electronics system performance in less space cannot always be satisfied solely by silicon integration; assembly and subassembly packaging must also play a role.

The latest efforts at increased package integration are currently referred to as System-in-Package (SiP)—also known as integrated passives.

In a SiP, one or more ICs are mounted on a substrate within a single package. Passive devices can be embedded in or mounted onto the substrate. MEMS and optical devices can also be incorporated within a SiP.

Different from MCM Concept

How does this differ from the largely failed MCM concept? Generally, inexpensive die are used in SiPs, making the failure of a single die—and thus, the SiP—less of an issue than it typically was with ""traditional"" MCMs.

(Under such conditions, of course, a device labeled as a SiP can hardly be considered a "system." But, why quibble?)

The assembly of a SiP requires additional processes and component logistics over the assembly of standard IC packages. One missing part precludes the assembly of the entire package.

By its nature, a SiP is a custom, application-driven device. Unlike traditional IC packaging, where the IC producer is typically the customer of the package assembler, OEMs are usually the assembler's assembler’s SiP customer.

Cellular telephones are one application for SiPs. Both Nokia and Ericsson have used SiPs in their phones. SiP design and assembly is offered by a number of companies, as described below.

Alpine Microsystems designs, manufacturers, and markets SiP products based on its patented Microboard substrate and DirectAttach packaging. Alpine’s MicroBoard substrates implement a microelectronic interconnect architecture, utilizing copper and low-k dielectric, combined with system-level design, software, and high density flip chipflip-chip assembly.

Amkor Technology Inc. provides both flip chipflip-chip and wire- bond capability and ball pitches down to 0.5 mm for its SiP products.

Additionally, the company offers extensive capabilities in handling GaAs, SOI, SOS,, and other RF and high-speed wafer technologies. The substrate used in the SiP can be either laminate or ceramic.

CS2, Belgium, offers thin film interconnection with embedded passives. This technology, which came as a technology transfer from Europe’s IMEC, is based on copper thin film and BCB (Dow) dielectrics. A very versatile process, the interconnection technology can be applied for digital applications or for analog, RF and microwave applications

Epson Electronics America/Seiko Epson offers a SiP, which it also calls a "folded MCM." Both die and capacitors are mounted on a flexible substrate, held on with anisotropic conductive film.

Each of the die protrude out on a "wing" of this flex tape, and each wing is folded in toward the middle area of the flex tape so that each die rests on top of the other in a compact square.

Intarsia offers a SiP with the die encapsulated on the top surface of a substrate laden with passive components. The result is a two-tiered product with active components on top and passives on the bottom. Intarsia refers to this product as a Functional Block.

IBM produces the HyperBGA, a package that allows up to 1657 I/O, has a flip chip interconnection, features a laminate substrate with surface surface-mounted capacitors and supports gigahertz frequency performance.

Ormet Corp. has developed a method of fabricating embedded passives within circuitry made from TLPS (transient liquid phase sintering) conductive pastes in a novel additive process.

Polymetric Insulator

The key to the technology is the use of a photo-patternable, polymeric insulator to define both circuitry and embedded passive components.

Silicon Bandwidth produces a SiP with molded passives incorporated into a single subassembly that rests on posts above the IC. The entire assembly is then sealed in a single package.

Electronic Trend Publications (ETP), San Jose, is a market research firm specializing in all phases of electronics manufacturing, from wafer fabrication through final assembly. Visit ETP's Web site at electronictrendpubs.com for more information. Contact Mr. Berry or Ms. Winkler by e-mail at info@electronictrendpubs.com or by phone at 408.369.7000.

 
 
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