Current Issue The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging November - December 2001 Email the editor

By David Francis and Linda Jardine, Contributing Editors

How did we determine which patents out of 350 were best? Our selection was largely subjective, based on our experience and our knowledge of the literature and the industry. The primary reason for the selection of each patent, however, is indicated at the front of that patent. (The patents are presented in no special order.)

Figure 1. The effect of void size on solder joint strain

1. Understanding the Causes of Voids in Solder Joints

This patent (Figure 1) was selected because it discusses a general problem that can be encountered by anyone in this industry, and because it indicates how the effect can be reduced or eliminated. The package manufacturer can make a package with perfect joints, yet this same package can fail prematurely due to poor assembly practices.

A standard way of joining solder-bumped devices to PWBs is to screen-print solder paste on the pads, place the device and reflow it. When heated, the flux in the solder paste volatilizes forming bubbles that escape mainly into the atmosphere.

Some of these bubbles, however, remain in the molten solder. Since these bubbles weigh less than the solder, they tend to move up through the molten solder and collect in the region where the solder is bonded to the package substrate or chip.

If the solder does not adhere well to the substrate or chip pad, these small bubbles can collect and create a large void.

In this patent, the company studied the effect of these voids on solder joint strain. The results are shown in the accompanying graph. Researchers found that small, uniform voids have little impact on strain for modest amounts of void area. As shown in the accompanying chart, a void area as large as 15-20% of the total solder area had about the same strain as a 2% void area. The strain produced by large concentration voids increased at a much faster rate.

The solution provided in this patent was to prevent the formation of concentration voids by first decreasing the heating rate for reflow soldering, which allows more time for the flux vapors to escape, and then decreasing the amount of solder paste to the minimum needed for a good bond.

Figure 2. Selecting stiffener TCE to minimize solder stress

2. Understanding the Role of the Stiffener Used in a TAB Ball Grid Array Package

We selected this patent (Figure 2), again, because it addresses a specific industry problem, it was well investigated and the solution was clearly presented.

It is also an example of how the package designer must understand where and how the packages are to be used to properly select the correct materials.

To be able to handle the TAB BGA throughout its processing, a stiffener plate is usually attached to the TAB frame or vice versa. This stiffener can be made of a laminate or metal, and it is chosen for reasons of cost, thermal dissipation or ease of manufacture, etc.

The parameter that is often overlooked is its specific TCE compared to that of the PWB on which it is mounted. If there is a TCE mismatch, the solder joints can be unnecessarily stressed.

Figure 2 shows the effect of a TCE mismatch between the package stiffener and the PWB on solder joint stress.

This is another case where the package can be well-designed, yet fail prematurely if placed on the wrong type of substrate.

Figure 3. Detecting misregistered or misstacked laminate substrates

3. Detecting Misregistered or Misstacked Layers

One key to running a high-yielding manufacturing operation is to prevent defective materials from entering production. The easier it is for anyone, operator, inspector or engineer to detect a defective part, the better.

This patent describes the use of pads that can be added to each layer of laminate to detect layers that are misaligned or misregistered. This same approach can be easily modified for other applications.

Figure 3 illustrates the two pads that are added to each layer and the results of a laminate stack that is correctly made as opposed to one in which the layers are misregistered and in the wrong order.

Figure 4. Wafer-level package with backside protection and solder joint support layer

4. Wafer Level Package with a Supporting Layer

This patent (Figure 4), was chosen because the manufacturing process is similar to the standard flip-chip process, and because it addresses the issue of backside protection.

The process described in this patent does not require an underfill. An underfill is normally used to reduce stress on the solder joint by spreading the stress over the entire joint rather than where it contacts the chip pad. Underfilling is undesirable because it adds extra cost and processing time.

The solution proposed in this patent is to apply a thicker supporting layer to the face of the die. Suitable materials are polyimide or BCB. The thickness added should be between 4 and 10 microns.

The via in the supporting layer is larger than the via in the underlying passivation layer. Enlarging this via increases the support area for the solder joint. The UBM is formed from any suitable conductive and solderable material such as NiV.

A protective coating is also applied to the backside of the wafer before it is diced. This coating protects against chipping, and can also provide ESD protection. Where the silicon is sensitive to light-induced carriers, the backside coating can provide light masking.

Figure 5. Wafer-scale package using double bumps

5. A Wafer Level Package (WLP) Using Multiple Bumps

This patent was selected because it uses a relatively simple set of low-cost processes to produce a WLP.

The pads on the wafer are bumped by plating or other processes (Figure 5). The plated bumps are column-shaped. A suitable encapsulant is screen-printed over the entire surface of the wafer, covering all bumps. To prevent trapping air bubbles in the encapsulant, screen printing is done in a vacuum or low-pressure chamber. The encapsulation thickness can vary from 2 microns to 2 mm. After printing, the encapsulant is cured.

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