Current Issue The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging November - December 2001 Email the editor

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The cured encapsulant is ground away until the ends of the solder columns are exposed. Conventional solder balls are then placed on the exposed columns using a suitable transfer method and reflowed. The final step is to singulate the wafer into individual packages.

In a variation of the above process, the encapsulant is applied by a dispensing needle. While it covers each solder column completely, there are valleys between columns. This approach allows for better under-chip cleaning.

Figure 6. A low-temperature bumping and joining process

6. Transfusion Bonding with Pre-Applied Underfill

We selected this package because it shows the blurring between flip-chip and chip-scale packaging methods (Figure 6). The bonding process occurs below the eutectic temperature of Pb/Sn and the process is environmentally safer by not using lead.

This patent contains several interesting processes. The first process is the use of thermoplastic underfill, applied while the die are in wafer form.

The second process is the use of a ball bump containing a flexible polymer core and which is plated with Ni/Sn/Bi. The Ni is the barrier and adhesion layer while the Sn/Bi is the solderable layer.

The third process is the use of transfusion bonding or the joining of metals below their melting temperatures. Parts can only be separated by taking them above their melting temperature. The coated balls are bonded to the wafer using transfusion bonding. In this process the wafer is heated, but pressure is applied to the balls by a cooled bonding tool.

After dicing, the devices are bonded to a substrate, again using transfusion bonding. In this step, the bonding tool is heated, and the balls first bond to the pads on the PWB. Continued heating causes the thermoplastic resin to soften and flow around the solder joints completing the process.

Figure 7. Filling blind and through vias with copper paste

7. Filling Narrow Vias with a Copper Paste

With increasing package I/O density, PWBs must keep pace, and the drilling and filling of board vias must continue to shrink in size. Whether the holes are drilled mechanically or with a laser, filling the vias so that they have a low resistance and a usable surface is increasingly important. This patent (Figure 7) describes a process for filling these fine via holes.

A suitable copper paste is applied to a thin support film. The support film is about 0.5 mils thick and the copper paste thickness is 5 mils. A suitable film material is polyethylene, but other materials can be used.

The paste containing film is placed on the PWB with the film side against the board. The stack is then placed in a laminating press where heat and pressure are applied. The pressure ruptures the film over the vias, driving the copper paste down into the blind or throughholes. Heating enhances the process.

After removal from the press the film is removed from the surface and any unwanted residue removed from the surface by grinding or other method. Additional surface metallization can then be applied as desired.

Figure 8. High-speed analog connection

8. High-Speed Analog Connection

This technology (Figure 8) was selected as example of a unique way of exchanging data with a chip other than through conventional connection methods.

In this patent an RF transformer is fabricated by photolithographically forming a co-planar inductor on the surface of the IC. A corresponding inductor is formed on the chip-scale package base by screen printing.

The two inductors are coupled by magnetic induction to form an RF transformer, which makes it possible to exchange signals in one or both directions.

The inductor on the IC has a diameter of between 100 microns and 1 mm, a thickness of 0.4-2 microns and between 4 and 25 turns.

The thick film inductor on the package base has a diameter of 1-3 mm, a thickness of 10-100 microns and between 4 and 25 turns.

Since there is no electrical connection between these two components, the normally required protection circuitry can be eliminated. Data can be exchanged at very high data rates.

Figure 9. High-performance interposer

9. High-Performance Interposer

The patent in Figure 9 was selected to illustrate that while some packaging methods are becoming simpler, others are becoming more complex.

As chip interconnect density increases, the close spacing of signal lines results in various types of interference, cross-talk and capacitive coupling.

When ground and power lines are routed on the same surface as the signal traces, they compete for space. The need to provide additional signal line shielding means increasingly less space available for signal lines.

In this patent, signal lines are routed entirely via the center layer. No power or ground connections are present on this layer. This results in an increase in the signal trace interconnect density of 1.4x.

Power and ground are only on the outer wrap around layer. This approach also allows a lower density design on this layer. The layers can be tested separately before being assembled.

Another benefit of this design is that most of the power and ground vias can be replaced with the edge wrap shown. This substantially reduces the number of vias required.

Figure 10. Wafer-level mutichip CSP

10. Wafer-Level Multichip CSP

We selected this CSP design (Figure 10), as illustrative of a number of 3D/stacking designs. While most approaches are based on stacking separated chips, this approach stacks one chip onto another chip which is processed to form a wafer-level multichip module package.

In a conventional MCM, the chips are spread out in an X-Y plane. This approach requires a larger substrate and package while offering reduced electrical performance. The process described in this patent is suitable for use in a small digital camera, where one chip is the CCD and the other contains the driver circuitry.

In this process, the smaller chip is processed in wafer form through bumping. It is then diced. The bumps are Au/Sn.

The second wafer containing the larger die includes a redistribution or interconnect layer on its surface that provides the connections to the smaller die and to the I/O pads. The traces used to connect to the smaller die have two open areas. The first is for the Au/Sn connection to the smaller die, the second is for attaching the I/O solder ball.

There is no TCE mismatch between the two devices, since they are both silicon. The trace inductance is very small due to the direct connection and a heat sink can be attached to the larger device for improved thermal performance.

Summary

These patents are among some of the best that were issued last year. There was not enough space to do justice to all of the good ideas that were granted, and a number of companies made outstanding contributions to this patent area. IBM again had the greatest number of patents, followed by Micron Technology.