Did you think leadframes were fading into oblivion? Consider that Amkor just lowered the typical leadframe package cost 20 percent from an estimated 0.2 cents/lead, thereby raising the cost of entry for wafer-level CSPs (WLCSPs). If package production levels were proportionate to press coverage and conference papers, leadframe packages would have disappeared over five years ago, replaced, first, by array packages and later by wafer-level CSPs, vying for many of the same market positions. But if hype automatically translated into reality, multichip modules would now be thriving in the mainstream. Remember, MCMs were going to bridge the connectivity gap between silicon and higher interconnection levels, back in the early '90s. Array Packages Then array packages came along (thanks to some bright engineers at Motorola) and went a long way toward filling that gap. WLCSPs are the latest and hottest array packages because of their performance and density advantages. Because of the economies of scale resulting from creating packages at the wafer level, there is the promise of lower cost. Note, however, that most of the volume runners have only peripheral solder bumps, fewer than 10, replacing leads. Moreover, 300 mm wafers are an emerging "stealth factor" that will increase the economies of scale even further for these mature, simple, very high-yielding devices in wafer-level packages. Today's reality is that, first, some 90 percent of IC packages still use leadframes, accounting for more than 50 billion units last year. Next, MCMs are an important niche. Finally, consider that WLCSPs are a fast-growing infant that still has a way to go before filling the leadframe package's market shoes. What are the factors driving the growth of WLCSPs? They possess three actual advantages over leadframe packages: 1. greater density (lower subsystem substrate cost), 2. higher thermal conductivity, and 3. faster circuit speed (lower parasitics). Is lower package cost also an advantage? Not today-WLCSPs have a hard time meeting that package 0.2 ¢/lead LF challenge. Whether WLCSPs will ever be cheaper than leadframe packages is a question that time and market development will answer. There are precedents that defy conventional reasoning: The cost analyses that say leadframe packages will always be cheaper. But maybe the question will turn out to be irrelevant. One precedent is CMOS, invented at RCA in 1962. Before 1984, NMOS (and some PMOS) ruled the roost. Then, the combination N- and P-cell construction began to push their progenitors (along with ECL bipolar) into IC oblivion. CMOS offered a 90 percent operating power reduction and required no power in the quiescent state. Originally, it cost twice as much as NMOS at the device level, but there were great systems savings. As CMOS moved into the mainstream in the 1980s, the cell size and price differential diminished, then vanished. Intensive, competitive R&D, which produced clever innovations, along with volume production, led to absolute market victory. A Model for Market Success That may be the future model for WLCSP market success. Today, however, some 90 percent of IC packages employ leadframes. At the very least, Amkor's high-density manufacturing and test process will help extend that leadframe package domination in most markets, because most markets are price sensitive. The competitive effects on WLCSPS will be felt even more strongly for packages with lead counts over 20 that require pad redistribution from peripheral to array, with its attendant increased process cost. The product portfolios of most Integrated Device Manufacturers (IDMs) include IC families in leadframe packages (QFPs, TSOPs, etc.), counted in mighty numbers. Estimates of these IC categories for 2000 included analog-about 40 billion units; memories, 10 billion; small-scale logic and MCUs, over 10 billion. Most of these ICs are produced by IDMs with a tradition of using their own captive packaging facilities-going back to the days when leadframes were all that was available for IC packaging-and outsourcing wasn't even in the dictionary. Generally, however, IDMs will not choose to invest in leadframe packaging improvements in an era of dynamic packaging change. Amkor, as the leading packaging foundry (approximately $2 billion in revenue last year), has the incentive to further improve leadframe packaging economics, since half of the company's revenue derives from leadframe package assembly and test. It's an effective strategy that should pay off in more outsourced business, as most integrated IDMs increasingly focus on design, fabrication and marketing. Amkor, with 5.1 billion leadframe devices produced last year, owned about 10 percent of the total market and about one-third of the merchant market. That's a good base for growth in healthy IC markets. In fact, the future transition to WLCSPs will almost certainly increase the outsourcing of mature leadframe package manufacturing by the IDMs. (And we should note that there are even leadframe schemes for WLCSPs.)
Matrix Assembly and Test The most visible (and key) manifestation of Amkor's two-year, $50 million leadframe development thrust is the standardized and increased size format. That format alone produces savings in materials (20 percent), labor, cycle time and floor space (50 percent). Amkor's parallel testing replaces singulated testing, yielding savings resulting from reduced indexing, and providing reduced test time, as well (as shown in the graphic). The end result is a 6x throughput improvement, reflecting triple the number of devices being handled at a time. Molding compound use, too, is reduced by over 30 percent. This represents an ambitious endeavor by Amkor that required extensive retooling at a cost of $200K-$400K each for 50 tools (accounting for much of that $50M). Questions that remain unanswered, for now, are licensing and industry standardization. These items are always the quandary of pioneers, raising additional questions of benefit vs. cost. Hardly a week goes by without the announcement of a new WLP. The prolific offerings are a major endorsement of the packaging technology, but how many will survive and/or thrive? To answer that question, we must consider the origins of WLP and the classes of the players. New niches are being enabled by WLP in new spaces that leadframe packages cannot even address. Most WLCSPs are a marriage between flip-chip-on-die interconnects, extended to wafers, and the CSP concept, but there are many variations. Tessera, San Jose, was an early CSP developer, with its reliable flexible interposer that was later adapted to wafer-level construction. Competitor FormFactor, Livermore, Calif., uses its Microspring, adapted from the Microspring's successful application in wafer test probes. So these two companires are exceptions to our generalization-that there is no flip-chip-on-wafer. But wafer-bumping leaders, the K&S Flip Chip Div. and Unitive, its major competitor, offer WLPs with bumps or discrete solder balls For truly high-volume wafer-level production, however, look to the IDMs. Maxim-Dallas Semiconductor's "1-Wire" (for 2-terminal clock devices), National Semiconductor's micro SMD, and now TI's NanoStar (initially for 5 I-O small scale logic) have developed the simplest, most cost-effective WLPs as competitive weapons to increase market share in device marketplaces. The Casio-Oki-IEP package is an important exception to our generalizations. These companies have jointly developed-and IEP offers to the world-a more elegant post and solder ball interconnect on wafer with redistribution for higher lead count devices. When you look at the Casio camera watch that the technology makes possible, you have to respect it. One final note-Casio-Oki-IEP was an early user of wafer steppers back in 1999. If we could follow stepper sales, we would know who the serious wafer-level packagers are.
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