With the advent of industry heavyweight TI's NanoStar package, wafer-level packaging (WLP) has established a beachhead in the semiconductor industry. In addition to TI, more than a dozen leaders including Casio, Dallas Semicon-ductor and National Semiconductor are shipping volumes of IC chips packaged at the wafer level. The movement's vanguard is concentrated in low I/O applications, including power conditioners and op amps. While it is building an entrenched position, WLP has not yet broken out of its beachhead in small-chip applications. 'Dressed-up Flip Chips' Cost reduction is the familiar imperative driving low I/O applications. Thousands of chips, packaged and tested on each wafer, are little more than dressed-up flip-chips. Typically measuring less than 3 mm on a side, they can be surface mounted directly onto circuit boards without the underfill needed to assure reliability in larger flip-chips. In addition to low cost and small size, electrical and thermal performance is an asset in the fast-growing wireless sector. But as we have learned, size and performance count for little in the high volume consumer market. Cost is everything! WLP achieves the lowest cost in the domain where chips can be finished without costly redistribution layers or complex bumping processes. Metal pads can be formed by electroless nickel plating, which avoids lithographic processing. Solder bumps are then formed by reflowing stenciled paste or solder balls. This simple, low-cost process is limited to chips below about 20 I/O, which do not require redistribution wiring. As the smoke clears, the perimeter of the wafer-level beachhead is becoming clearly delineated to encompass small, low I/O chips. Solder balls spaced 0.5- 0.8 mm apart allow for wiring in standard 0.1mm line/ space circuit boards. These simple chips do not need to be burned-in before final test on the wafer. A thin surface layer protects the chip against corrosion, but not necessarily against alpha particles. These low cost processes are very effective and high yielding for simple chips. Advances in wafer-level technology are needed to break out into broader applications. The extension to larger-size chips requires flexible contacts between chip and substrate to accommodate thermal strains. More than simply connecting the dots, package design must allow for differential expansion of more than 5 µm between chip and substrate in DRAM applications. Hitachi recently presented results of its work on a low-cost, wafer-level package by using flexible leads to connect pads to solder balls resting on a stress relaxation layer. The 54- lead Hitachi test chip demonstrates acceptable reliability for chips 10 mm on a side-sufficient for memory applications. Another approach, publicized by Motorola and Advanced Interconnect Solutions, employs elongated solder balls to relieve thermal stresses in larger chips. On another front, substrates with reduced CTEs are being evaluated as a way to reduce thermal stress in applications such as memory cards. IBM's HPCC, slated for production in Shanghai, utilizes a metal-core substrate to reduce CTE and associated stress. With many viable options, there can be no doubts that WLP will extend to large chips as reliability problems are resolved. Moreover, with advances in process maturity and cost reduction, WLP is poised to invade the DRAM sector as costs reach parity with conventional packaging. Because of redistribution costs, volume production is currently concentrated in the low I/O chips. As redistribution costs decrease, higher I/O chips will be viable candidates for WLP. Performance Enhancements And with decreasing costs, designers will use added wiring capability for performance enhancements, such as clock trees and power-to-ground distribution. Beyond package cost, other factors limit adoption. To reap the full benefits of wafer level packaging of DRAM and other complex chips, effective solutions for wafer-level burn-in and final test are needed. At the systems level, advances in microvia substrates, thermal management and design methodologies, among others, will pace WLP as it proliferates into broad applications.
|
Copyright © 2001