By Tim Jensen and Dr. Ronald C. Lasky, Indium Corp. of America, Utica, N.Y.
If you are not yet assembling CSPs, you will be soon. The CSP's small size (<1.1 x the die dimension), its need for burn-in and testing, and die placement using standard SMT processes, have made the CSP a preferred part of the IC packaging repertoire. Assembled cost comparisons indicate that CSPs are a lower cost answer than most direct chip attach (DCA) approaches.1 These benefits have resulted in giving CSPs the highest compound annual growth rate (CAGR) in the industry at 35 percent/ year, as shown in Figure 1.
High Yield Assembly with CSPs A systematic approach to SMT assembly considers:
The inputs to the mounting process for CSPs consist of the CSP components, the PWB, the solder paste, the stencil and the squeegee. For brevity, we will assume that the assembler starts with JEDEC or similar standard CSPs (which conform to receiving inspection criteria) and an IPC-conforming PWB. (For a source of general information on SMT assembly see reference 2.) We will also assume that the CSP's solder balls, as well as the pads on the PWB, are wettable by tin-lead eutectic solder. However, we will discuss solder paste and stencil requirements in detail. Although we don't want to minimize the importance of the placement process, typically >70 percent of defects are the result of printing and reflow-related problems. Hence, we will thoroughly analyze printing and reflow-related defects. Procedures are required in all processes for orderly and effective production. Accordingly, we will discuss the implementation of statistical process control (SPC) for the stencil printing process, which we feel is the most important control procedure for successful assembly. The output is clearly an assembled PWB that meets the requirements. The collection of failure analysis data is one of the fundamentals of a continuous improvement program. CSP Mounting Solder paste is probably the most critical input to the CSP mounting process, assuming that the CSP and PWB conform to their respective specifications. We recommend using a no-clean Type III solder paste for CSP mounting. The Type III designation refers to the size distribution of solder powder used to make the paste. The powder can be manufactured via several different processes. (The interested reader can learn more about solder powder and its manufacture in reference 3.) A Type III paste consists of powder which has no particles greater than 50µ. In addition, 80 percent by weight of the particles must be between 25-45µ with fewer than 10 percent by weight smaller than 20µ. More than 95 percent of today's pastes are made using Type III powder. Type III pastes are suitable even for 0.5mm pitch, the finest pitch employed for CSP today. Type IV pastes (made with finer particle sizes) are not recommended except for ultra fine pitch (UFP) assembly, with lead spacings of 0.4mm or less. The use of Type IV paste when not required will result in increased solder balling and voiding. These failure mechanisms become more pronounced because the finer particles have more surface area and will be more likely to oxidize. In addition, it may be more difficult to obtain stencil-printing consistency with Type IV pastes. No-Clean Solder Paste When populating PWBs with CSPs, a no-clean solder paste provides the best opportunity for success. There are at least three reasons why no-clean pastes are recommended over water-washable pastes: 1. The minimal CSP component stand-off of water-washable pastes makes cleaning more difficult. 2. No-clean pastes typically offer improved printing, especially through smaller stencil apertures such as those for CSPs. 3. The lower flux solids in no-clean pastes result in less voiding in the CSP solder joints. Unfortunately, all Type III no-clean solder pastes are not created equal. For successful CSP attach, design of experiment4 (DOE) techniques should be used to evaluate solder pastes. We will discuss using DOE later. Stencils The industry is moving toward laser cut/ electro-polished stencils.5 This method of manufacturing stencil apertures produces relatively smooth walls and allows for a consistent solder paste deposition. Electroformed stencils also possess smooth aperture walls, but can be more expensive than other stencil types.6 Both of these stencil manufacturing methods are good choices for device assembly using CSP technology.
Proper stencil design is crucial to successful CSP attach. The "area ratio," or the ratio of the area of the stencil aperture opening to the area of the sidewalls, should be greater than 0.66. This criterion helps assure that the printed solder-paste deposit ("brick") adheres to the PWB pad and not the stencil sidewalls. Although the guideline of >0.66 for an area ratio is standard, recent studies show that an area ratio as low as 0.5 may be possible using electroformed stencils. (See Figure 2 for area ratio calculation guidelines.)
As an example, let us assume that we are mounting a 0.5mm (20 mil) pitch CSP. Industry standards recommend that the pad on the PWB should be 12 mils (0.3 mm) and the aperture 10 mils (0.25 mm). One concern is that if the stencil is a typical 5 to 6 mils thick, the area ratio is, at best, 0.5. The stencil thickness needs to be reduced to less than 4 mils to achieve the desired area ratio of 0.66. Because a stencil that is 4 mils thick overall may not deliver enough paste for the other components on the board, a step stencil may be required5. We strongly recommend using metal squeegee blades. These are proven to provide the most consistent solder paste print deposition. An exception to this rule would be if a step stencil is used. In that case, a polyurethane squeegee may lengthen the life of the stencil and provide better fill of the stepped-down apertures. |
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