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November - December 2002
The International Reference for Chip-Scale Electronics, Flip-Chip Technology, Optoelectronic Interconnection and Wafer-Level Packaging
November - December 2002
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Publisher's Letter
Farewell to 2002
Assembly Lines
Doing Business in Japan? San Jose's Tessera Looks to Licensees, Partners
Opto-Electronically Speaking
When the Economy Rebounds, So Will Opto, MEMS and Nanotech Excitement
Standards
Testing Packages with Lead-Free Finishes? MRT Reflow Standard Is Finally Revealed
On Test
Parts, Pins, Parallelism, BIST and DFT - Pieces of the Final Test Conundrum
Industry News
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FSA Suppliers Expo Album
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Opto/Nanotechnology
Packaging Foundries
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Editorial Index
Features
Solder Ball Placement: Machine Makers and Users Are Preparing for Smaller Ball Diameters
Solder Ball Placement Equipment Directory
Defect Inspection: Core Technology Choices Range from AOI to Lasers to Moiré Interferometry to Scanners
Automated Defect Inspection Systems Directory
Assembling Chip-Scale Packages with High Yields Requires Care with Printing and Reflow Processes
Editorial Index for 2002
Test-on-Strip: What It Takes, What It Offers Users
Wire Bonding: the Preferred Interconnect Method
Tools & Technologies
Solderless Sockets for Evaluation Test and more...
Patents
Invention Describes How to Form Wafer-Level Hermetic Packages
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