A recurring reader question relates to the interaction of device pin counts and how they affect test requirements when and BIST (built-in self test) and DFT (design for test) are introduced. A Critical Issue with 300mm This issue is very critical with 300mm wafers and 0.13 micron technology. Many of these devices sport pin counts ranging from hundreds to over 1000. If functional (mission mode) testing is used for these components, it is difficult to test them at all, let alone in parallel. For smaller pin counts and die, the scaling can result in fairly staggering die-per-wafer counts. It is not uncommon to hear of products with over 10,000 die on a 300mm wafer. The functional throughput equation for SOC and other digitally dominant devices in this arena seems poor. Engineers have told me of wafer test times over 28 hours for one wafer when testing the die singly! A way to attack this issue is to reduce the number of pins per device needed for test via structural test methodology.
This pin reduction requires a design that includes special, low overhead test circuits in the device. This circuitry falls into two main categories: DFT and BIST. Both present very different implications for circuit and system design, although both are typically accessed through the same port. The standard port is a three-pin interface: clock, data-in and data-out. Theoretically, we could design the largest devices and test them with just power, ground and this three-pin interface, called a "scan tap." Practically, the port is usually duplicated or widened to allow for higher throughput in and out of the device. The total port interface pin count usually ranges from 3 to 64 pins. Now, we can take the pin count of the highest capacity ATE available for digital components-1536 channels-and divide by the number of pins per device required for this scan-based test. The number of data pins used for the ports influences the number of devices to be tested in parallel. These relationships are shown in the figure. The Effect on Probe Cards A related issue is the effect this produces on probe cards. In general, a high volume device requires that all the available tester and probe capacity be used to gain the greatest number of devices tested in parallel. A lower-volume device may allow for different choices, since the cost of the high pin count probe card and interface hardware may not properly be amortized on low volume or short run devices. The latter, however, is more of an economics study instead of a technical issue, however. Structural test with scan access, meanwhile, allows the digital component supplier the efficiency in test that only memory suppliers were able to achieve previously. This revolution has been a long time coming and will continue forward, driven by our tight economic times.
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