PATENT NUMBER: 6,429,511 ASSIGNEE: Agilent Technologies, Inc. INVENTORS: Richard C. Ruby, Tracy E. Bell, Frank S. Geefay and Yogesh M. Desai TITLE: Microcap Wafer-Level Package This patent describes processes that are more typical of MEMs packaging than conventional semiconductors. The patent, however, presents a number of unique processes. Described is a method of forming a microcap for an active device, a sensor or a combination of the two. Hermeticity is a requirement, and the joining process must be an improvement over methods currently used. Current joining methods are silicon-to-glass anodic bonding, silicon-to-silicon fusion bonding and soft-metal bonding. Some of these processes employ high voltages that are detrimental if electronic circuits are present. Others require higher temperatures than some of the materials can withstand. If glass frit is used, the area required for good bonding results in a much larger device. The processes used in this patent are standard ones found in typical semiconductor facilities. While both wafers are silicon, the process can be used with other wafer materials. Both base and cap wafers, however, should be of the same material to prevent TCE-related problems.
The Invention The base wafer contains an active circuit, passive sensor or other component(s) that must be hermetically sealed. The base wafer is processed to contain gold pads where required. The cap is processed in wafer form and is either a nonconductive material or a high-resistivity semiconductor wafer, such as single crystal silicon. A blanket seed metallization layer is deposited on the wafer and patterned with thick photoresist so that the metal gasket walls can be plated. The metallization is typically three layers, such as Cr, Ni-V and Cu. The gasket pattern is a perimeter seal ring with ring-shaped areas around each bond or contact pad. After plating the gasket walls, the photoresist layers are removed and the exposed seed layer is etched away. Another thick photoresist layer is applied and patterned to expose the hole locations for the external connections. The silicon is etched using a dry plasma process in order to form high aspect ratio holes approximately half way through the 8-mil thick wafer. An alternating process of etching and depositing a polymer on the etched walls is used to minimize undercutting. The photoresist is removed and the wafer cap is aligned to the base wafer and bonded using both pressure and temperature. The process is described as cold welding, but a temperature up to 350°C is also mentioned. After sealing, the top cap wafer is thinned to expose the openings to the bond pads on the base wafer. The cap thickness after thinning is less than 100 microns. In one version, the holes in the top wafer are made sufficiently large so that a wire bond capillary can reach the pads on the base wafer to make the wire bond connection. In another approach, the top surface of the top wafer is metalized with a seed layer so that the via connections can be plated. The metalized surface can also be patterned to form bond pads on the top surface of the top wafer. The devices are singulated by sawing. Summary This patent describes a means to form a hermetic package at the wafer level. It is somewhat surprising, however, that external bump connections are not described.
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