November- December 1998
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Reducing The Thermal Resistance of CSPs and Flip-Chip ICs
-By David Francis arid Linda Jardine
-International Interconnection Intelligence, Montara, Calif:|
PATENT NUMBER:
5,729,052 ASSIGNEE: International Business Machines INVENTORS: William R. Tonti, Jack A. Mandelman, Jerzy M. Zalenski, Toshiharu Furukawa, Son v. Nguyen and Dureseti Chidambarrao TITLE: Integrated ULSI Heat Sink |
This approach, however, has shortcomings, since an interface layer is added between the die and the heat spreader and a second interface is placed between the heat spreader and the heat sink. Because of the small package and die sizes involved, these interface layers are not very efficient, which limits the amount of heat that can be removed efficiently from the back of a package or chip.
Significant ImprovementThe approach described in the IBM patent offers a significant improvement in the heat removal process. The patent breaks the heat removal process into the intrinsic and extrinsic regions.
The intrinsic region deals with removing heat from the active surface of the chip to the back surface of the IC, heat spreader or package surface. The extrinsic region deals with the heat flow into the heat sink and its transfer into the ambient air.
This patent claims improvements in the intrinsic values by 202x and an extrinsic increase of 160x.
These improvements are based on a flip-chip device mounted in a ceramic PGA (CPGA) with thermal adhesive applied between the back of the chip and the metal lid and thermal grease placed between the lid and the heat sink.
The thermal resistance of this CPGA package is about 2 degrees C/W. This is based on a package k of 0.7 and a thermal adhesive k of 1.7. The thermal resistance is obtained by taking the reciprocal of the sum of the kA factors where A is the cross-sectional area for each layer in the thermal path and k is the thermal conductivity of the material. This is intrinsic Thermal Resistance.Because the intrinsic thermal resistance in the CPGA example is so poor, the external resistance of the heat sink to the ambient does not materially change the intrinsic thermal resistance.
Thermal resistance can be reduced by increasing the thermal conductivity of the various materials involved and/or by increasing the cross-sectional area. If the intrinsic thermal resistance can be significantly reduced, it will also be necessary to improve the external value to take full advantage of the performance improvement.
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| Figure 1. The backside of the wafer shows the abraded surface that has been deposited with Al, Cr, Cu and planarized. The surface is then coated with solder. |
The backside surface area is then is increased by etching or by sand blasting. The roughened surface is oxidized and deposited with a layer of aluminum followed by chrome. Copper (or aluminum) can then be deposited to fill the voids in the backside surface. This is followed by chemical-mechanical polishing (CMP) to planarize the surface.
The last step is to apply a layer of solder or gold eutectic material onto the surface and reflow it. The k factors are 205 for aluminum and 63 for lead/tin solder. Since the surface area has been increased by a factor of 2, the new intrinsic thermal resistance is now 0.01 degree C/W, a 202x improvement over the standard process.
The protective layer(s) applied to the front surface is removed before the wafer is scribed.
The same process used on the back surface of the wafer can also be used on the attachment surface of the heat sink. The result is that the external thermal resistance drops from 205 to 0.013 degree C/W, an improvement of 160x over the untreated method.
An additional benefit of this process is that the ability of the heat sink to resist delamination from the IC is about 2.5x higher than if it were mounted to a standard backside IC surface.
The type of solder used in mounting the device to the PWB must be taken into account when selecting the solder used for the interface layer between the IC and the heatsink.
In some cases, it may be desirable to permanently attach the heat sink to the die, thereby providing an easier h a n d I i n g method.
We believe that there is a better material to use than solder in this application. A company called D i e m a t (Topsfield, Mass.) has developed a high thermal conductivity thermoplastic material that has comparable thermal conductivity to that of solder and offers a much lower cure temperature.
Using this material will allow the heat sink to be placed after assembly. If it becomes necessary to remove the heat sink in the future, it can be easily removed by heating below the solder reflow temperature.
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| Figure 2. Planarization appears unnecessary with the method described in this patent, because the amount of solder is sufficient to compensate for any surface uneveness. |
Conductive thermoplastics are reworkable because the material does not cross-link like epoxies. The only requirement with this type of material is that it must be wet when joining new or reworked parts. These thermoplastics are available in the temperature range from 150 to 200°C.
While the process described in Figure 1 uses sandblasting, other processes can be employed. One method patterns the back surface with grooves to increase the surface area. This operation requires masking and etching steps.
The text of the patent indicates that copper or aluminum is deposited or plated on top of the chrome layer and then planarized. This is the flat surface shown in Figure 1.
The graphic in the patent shows a figure similar to that of Figure 2. In this figure, it appears that planarization may not be required. The amount of solder applied to one or both surfaces should be aufficient to fill any surface unevenness.
Because solder has a lower thermal conductivity than copper, the use of a larger volume of solder may degrade the degree of improvement obtained.
International Interconnection Intelligence is a market and technology research company specializing in the semiconductor packaging and interconnection areas. Contact the authors at iiil@ix.netcom.comor 650.728.5270.