November- December 1998
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CSP Reliability Studies Performed with Combined FEA and microDAC Measurements
Finite element analysis (FEA) and experimental strain evaluations are proving to be effective methods for revealing failure mechanisms and problems in manufactured test structures.
-By Drs. Dietmar Vogel, Juergen Auersperg and Prof. Bernd Michel of the Fraunhofer Institute for Reliability and Microintegration (IZM), Berlin, and Dr. Rao Mahidhara, Chip Scale Review
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| Figure 1. Flip chip and different types of CSPs investigated by FEA |
The thermo-mechanical reliability of advanced electronic packages, such as CSPs, is one of the main reasons for adopting this technology in products. Various kinds of inhomogeneities, including localized stresses and thermal mismatch between several components, can lead to interfacial delaminations, chip cracking, fatigue of solder interconnects and, finally, to package failure.
Nonlinear finite element simulations which respect the nonlinear, temperature and rate dependent behavior of different materials used (metals, polymeric and solder materials), as well as experimental investigations, have been employed for failure analysis.
The development and application of different failure models (e.g., thermal fatigue, lifetime predictions by CoffinManson type equations, integral fracture mechanics approaches- J-, J-, AT. integral- and evaluation integral- and evaluation of critical regions, respectively) are reviewed in this paper and illustrated for specific applications. Additionally, the simulation of damage growth in solder interconnects by an automatic adaptive finite element technique was performed using inherent local damage models to validate crack and damage models and is detailed here.
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| Figure 2. Lifetime estimation for different CSP concepts, thermal cycling (see also Figure 1.) |
Combined finite element analysis and experimental strain evaluations have been certified as effective methods for revealing failure mechanisms and problems in manufactured test structures. As a result, these methods of evaluation are being employed in predictive engineering approaches.1,2
Nonlinear FEA affords a precise description of thermal deformation behavior of assemblies if, and only if, the physical characteristics of the applied materials and the geometric description are known.
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| Figure 3. A single solder ball analyzed by FEA |
Nonlinear FEA also provides the basis for the evaluation of strongly localized stress/strain fields in thermally-loaded assemblies for several adapted failure models such as CoffinManson type relations and integral fracture mechanics concepts -- J-, J-, AT* integral. A combination with experimental investigations helps to locate relevant failure mechanisms and produces sometimes essential information about the actual package behavior not described by the applied mechanical model and generally makes FEA more trustworthy.
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| Figure 4. J-direction at several crack positions (prescribed crack path included in an outermost solderball of an FC-BGA |
The finite element simulation of the thermo-mechanical behavior of microelectronics assemblies assumes models of continuum mechanics ("homogenization" of usually multiphase microstructures). Approximate models should fit the multiaxial-loaded material to nonlinear uniaxial results from experiments. In reality, however, dependencies on microstructure, differences between tension and shear test and differences between results obtained from specimens of different sizes (mm or um scale) exist. Missing or insufficient documentation of measurement results and the preloading history of the specimens investigated is often an obstacle when comparing results with those from experiments.
Under all loading conditions, the stress/strain situation in microelectronics packages is characterized by inhomogeneities with extreme local concentrations on sharp edges, material interfaces (bimaterial edges, free edges), and defects (voids, cracks, lattice defects). Locations of higher stress or strain concentrations are frequent starting points of fatigue cracks. A finite element model has to take into account such inhomogeneities, because quality approximation depends on mesh density and the types of finite elements used.
Local and global temperature gradients and accelerated temperature cycle test conditions are the most important loading situations in microelectronics applications. Therefore, a nonlinear coupled field concept must be utilized in finite element simulation modeling, including the temperature dependent elastic-plastic behavior of metallizations, the nonlinear constitutive law with rate dependent creep and rate independent plasticity of solder interconnects and viscoelastic behavior of underfill and encapsulants.
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| Figure 5. Normalized C*-value vs. normalized crack length in an outermost solder ball of an FC-BGA for different board materials |
To evaluate results obtained by the FEA from the point of view of thermo-mechanical reliability, usually the concept of Coffin-Manson is utilized, assuming that either the accumulated equivalent creep strain amplitude 3 £ acc
or the averaged visco-plastic strain energy AWacc (both accumulated during one thermal cycle) are employed as measures for the damage4
In the formulas above C, D, n and m are materials constants, AW acc is the accumulated visco-plastic strain energy, V the volume of a finite element and Nf is the number of mean cycles to failure. These approaches take into account that some field variables, like the accumulated equivalent creep strain amplitude E acc become singular on solder edges and cannot be utilized as a local measure of damage.
The first approach bypasses this problem by observing the behavior of Eacc along the crack path expected; the second by averaging over some finite elements surrounding a singularity.Various types of CSPs have been analyzed by the authors, employing the first approach. Comparison of the estimated lifetime has been used to optimize electronic packages from the point of view of their thermomechanical reliability (see Figures 1 and 2).
Integral Fracture Mechanics ConceptsField coupling and nonlinearities of fracture phenomena in many microelectronics applications require additional successful approaches. Because of the strong localization of damage and fracture processes and the existence of several damage mechanisms, the utilization of the so-called generalized integral fracture concepts seems to be well suited to describe fracture behavior in the field of "fracture electronics."5
The very well known J-Integral from Rice, which describes whether a crack starts or not, is unfortunately coupled with the potential character of the strain energy W. This leads to restrictions, for use in applications, which simulate thermal cycling of assemblies with some (incrementally) elastic-plastic materials. In order to overcome this problem, the J-Integral from Aoki, Kishimoto, Sakata 6
and the ATk -Integral from Brust, Nishioka, Atluri, Nakagaki 7are much more suited. And last but not least, the C*-Integral from Landes and Begley is most favored for crack propagation stability evaluation in case of creeping materials
As an example the deformation and failure behavior of an outermost ball of a FC-BGA (Figure 3) has been investigated by FEA, using a global-local modeling technique.The creep law of the soft solder assumes that the total strain rate is a sum of the elastic, plastic, creep and thermal strain rate.
The stress/strain rate relation given by Hacke et al.8 is expressed bywhere the first term stands for super plasticity (grain boundary sliding) and the second for matrix flow. C describes related coefficients, TÑthe absolute temperature, ~Ñthe shear stress, RÑthe gas constant, nÑthe stress coefficients, dÑthe grain size, pÑthe grain size exponent.3
The J-vector is not directed to the path of highest accumulated creep strains (diagonally through the ball), but it points to the interface between ball and pad (Figure 4). This fits to the crack path, observed in reality for the particular package.Figure 5 shows a rapid increase of C* (first crack has a real length of 10 um) and saturation during later crack growth. The highest values can be observed for FR-4 as board material, the lowest for Al2O3.
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| Figure 6. Damage propagation at the corners of a solder ball of a FC-BGA under thermal cycling load |
but utilizing i- T* - and C* - integrals, shown before
instead of K and J. For that reason, constants like n, k, C or D have to be considered by coupled numerical and experimental investigations.
Damage Model
One important problem in lifetime prediction is the changing stress situation during failure progress, due to an unloading effect which causes a softening of the entire structure if a crack or damaged zone is growing. For that reason, we carried out a simulation of damage growth in solder interconnects, taking into account the stress redistribution mentioned.
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| Figure 6. Damage propagation at the corners of a solder ball of a FC-BGA under thermal cycling load |
Figure 6 demonstrates damage propagation in a ball of an FC-BGA under thermal cyclic loading, which was carried out by utilizing local visco-plastic work (accumulated during tension) as a measure of damage.
Figure 7. Dashed lines represent the expected deformation for thermal load of this µBGA package.
This concept of finding damage paths, also utilized by Ju et al.,9 demonstrates the advantages of a combined description of material deformation and damage. A disadvantage of this material deformation and damage. A disadvantage of this approach may be, that the user has to simulate 1000 cycles or more to predict the lifetime of a whole package. For this reason, a combination of all the methods outlined here is usually preferred.
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| Figure 8. microDAC measurement (SEM imaging) exhibits, of shear strains in an outermost solder ball of a thermally loaded µBGA (250C 145°C). |
Deformation Measurements
MicroDAC is a displacement and strain field measurement method. Incremental displacements and strains on specimen surfaces are computed from digital micrographs of different object load states. Small mutual displacements of characteristic image patterns are used for displacement field extraction. Mechanical or thermal loading stages for the object under investigation are integrated within the microscopic equipment. At present, mainly scanning electron, optical far field and laser scanning microscopes are used to capture images of loaded specimens. Underlying computer algorithms, measurement equipment and the capability of microDAC have been described in detail in several papers.'° " (Reference l0 contains more detailed comparisons between FEA and microDAC results aimed at an improved stress/strain analysis.)
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| Figure 9. This microDAC measurement (SEM imaging), shows strains (perpendiculat to the board direction) in an outermost solder ball of a thermally loaded µBGA (25°C 145°C). |
Tessera's µBGA package concept has led to one of the first successful CSP implementations. Figure 7 shows a scheme of the package. One of the key problems to be solved for chipscale packages mounted on low cost organic substrates is an appropriate accommodation of the thermal mismatch between substrate and silicon die.
The µBGA package relies on a compliant elastomer layer between the die and the flex carrier with the solder balls to eliminate thermal mismatch. Flexible curved bond ribbons connect the die pads to the solder balls.
The compliant elastomer layer and the flexible bond ribbons provide for a thermomechanical decoupling between die and substrate. Consequently, underfilling of the package-to-board gap is not needed to guarantee assembly reliability.
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| Figure 10. Rigid carrier CSP under investigation |
For that reason, microDAC strain measurements inside solder balls have been performed on FR-4 mounted packages. The assembled packages were cross sectioned and carefully ground along the peripheral solder ball line. To avoid any mechanical restrictions from the embedding epoxy during measurement, no specimen embedding was applied. A temperature profile with a nearly linear increase from room temperature to a temperature over 100°C within approximately 20 min was realized. Thermal loading and image capture were performed within a SEM system.
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| Figure 11. Common CSP and PC board warpage due to specimen heating from room temperature tpm to 90°C, shows optical microDAC measurement displacement contourlines (with displacement perpendicular to board direction) |
Figure 9 depicts the strain map for the component perpendicular to the board direction. Maximum values are on a level of approximately 1% in the solder, i.e., somewhat higher than the unrestricted solder expansion would be. This value is typical for underfilled eutectic solder-based flip chips of medium size."
Rigid Carrier CSP Measurements
Another approach to chip-scale packaging, introduced by different manufacturers, makes use of rigid substrate interposers. Again, the thermal mismatch between the die and the PC board must be handled by the package to provide aufficient reliability. Figure 10 presents the scheme of the rigid carrier CSP analyzed at the Institute. For the investigated version, both flip-chip bumps and package solder balls were not stressed over a certain level to avoid solder fatigue. On the other hand, warpage of the assembly, introduced by the mismatched thermal material, is an essential issue for package reliability.
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| Figure 12. This microDAC measurement (SEM imaging)displays, Solderball strain (direction perpendicular to board plane) on a rigid carrier CSP due to assembly heating from 23~,C to 1180C. |
Conclusion
This paper illustrates the advantages of several FEA and microDAC techniques for evaluating mechanical reliability of solder interconnects in advanced packages. Some examples in the fields of thermal fatigue and lifetime prediction of solder joints, integral fracture mechanics concepts, local continuum damage modeling and local deformation analysis have been outlined for further discussion from the point of view of lifetime prediction of advanced electronics packages.
References- 1. J. Auersperg, D. Vogel, et al., "Reliability Evaluation of Chip-Scale Packages by FEA and microDAC," Proc. of Reliability of Solders and Solder Joints Symposium at 126th 6, Orlando, Fla., February 1997, p. 439
- 2. D. Vogel, J. Caers, et al., "Advanced Deformation and Failure Analysis on Flip-Chip Assemblies," Proc. of Micro Materials '97, Berlin, Germany, April 1997, p.913.
- 3. A. Schubert, R. Dudek, et al., "Materials Mechanics and Mechanical Reliability of Flip-Chip Assemblies on Organic Substrates," Proc. 3rd Int. Symposium and Exhibition on Advanced Packaging Materials, Braselton, Gal, March 1997, p.106.
- 4. R. Darveaux, "Solder Joint Fatigue Life Model," Proc. Symp. on Design and Reliability of Solders and Solder Interconnects at 126th TMS Annual Meeting & Exhibition, Orlando, Fla., Februrary 1997, p.213.
- 5. B. Michel, T. Winkler, et al., "Fracture ElectronicsÑApplication of Fracture Mechanics to Microelectronics Systems and Chip Packages," Proc of 9th Int. Conf on Fracture (ICF 9), Sydney, April 1997.
- 6. S. Aoki, T. Nishioka, et al., "Elastic-Plastic Analysis of Cracking in Thermally-Loaded Structures," Eng. Fract. Mech.,Vol. 16, No.3, 1982.
- 7. F. W. Brust, T. Nishioka, et al., "Further Studies on Elastic-Plastic Stable Fracture Utilizing the T*- Integral," Eng Fract. Mech., Vol. 23, No. 3, 1986, p. 551.
- 8. R L. Hacke, A. L. Sprecher, et al., "Thermomechanical Fatigue of 63Sn37Pb Solder Joints," in J. H. Lau, Thermal Stress and Strain in Microelectronics Packaging, Van Nostrand Reinhold, New York, 1993.
- 9. S. H. Ju, B. l. Dander, et al., "Life Prediction of Solder Joints by Damage and Fracture Mechanics," lourn. of Electronic Packages, Vol. 118, Dec.1996, p.193.
- 10. Vogel and Auersperg, "Deformation Analysis of Flip-Chip Solder Interconnects by microDAC," Proc. of Design ~ Reliability of Solders and Solder Interconnects at 126th TMS Annual Meeting & Exhibition, Orlando, Fla., Februrary 1997, p.429.
- 11. B. Michel, D. Vogel, et. al., "The microDAC MethodÑa Powerful Means for Microdeformation Analysis in Electronic Packaging," Proc. of Symposium on Applications of Experimental Mechanics to Electronic Packaging at the 1997 ASME International Mechanical Engineering Congress and Exposition, Dallas, November 1997, p.117.
- 12. D. Vogel, E. Kaulfersch, et al., "Microdeformation Analysis of Packages and Interconnects by the microDAC Method," to be published in Proc. of Mechanical Reliability of Polymeric Materials eF Plastic Packages of IC Devices Workshop, Paris, November, 1998.
Dr. Vogel received his Ph.D. in physics in 1980 from the University of Petersburg, Russia. Since 1993, he has been working at the Fraunhofer Intitute for Reliability and Microintegration (IZM). in the Department of . Mechanical Reliability and Micro Materials, Berlin. Readers may contact him at d_vogel@izm.fhg.de or 49+30.46403.214, fax49+30.46403.211.
Dr. Auersperg received his Ph.D. in applied mechanics in 1980 from the Technical University of Chemnitz, Germany. He joined IZM as a senior scientist in 1996, working in the Dept. of Mechanical Reliability. His specialities are nonlinear finite element simulation, fracture and damage mechanics, fatigue and failure analysis. Contact Dr. Auersperg at auersprg@izm.fhg.de or 49+30.46403.214, fax 49+30.46403.211.
Dr. Michel received his Ph.D. in physics from Martin-Luther University in Halle, Germany. In 1993, he joined IZM and was named head of the Department of Mechanical Reliability. He is Chairman of the International Micro Materials Conferences. Contact him at
michel@izm.fhg.de or 49+30.46403.200, fax 49+30.46403.211.
Dr. Mahidhara, Chip Scale Review's Technical Editor, earned his Ph.D. in materials sciences from the Universi.ty of California, Davis, and was formerly Tessera's Manager of Joining Technology. His extensive industry experience includes posts as project manager at Cypress Semiconductor, San Jose; Research Engineer at the Burlington Research Laboratory at Raleigh, N.C. and Staff Engineer at IBM Microelectronics, Hopewell Junction, N.Y Contact him at rmahidhara@aol.com.