Test Strategy-A Test Strategy to Verify the Reliability of Chip-Scale Packages (continued)

November- December 1998 - ChipScale Review

November- December 1998

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A Test Strategy to Verify the Reliability of Chip-Scale Packages (continued)

Thermal Gradients

When an assembly is exposed to thermal shock, the large transient thermal gradients induced by the rapid temperature change will cause warpage of both components and PWBs. 9 The warpages result in tensile and shear stresses, where the tensile loading dominates. Even assemblies with matched CTEs will exhibit solder joint failure when subjected to thermal shock.

In contrast, thermal cycling results mainly in shear loads, and failures occur from an interaction of shear fatigue and stress relaxation. Wearout would not occur on assemblies with matched CTEs (if they could be manufactured). Consequently, thermal shock testing for purposes of evaluating solder joint reliability is only appropriate if thermal shock is indeed a field condition encountered by the product, which is a very unusual condition.

Even if a machine is exposed to very fast temperature changes, as may happen if it is taken from outdoor to indoor conditions, or vice versa, the assemblies inside the machine will not be subjected to fast temperature changes. Hence, only thermal cycling is adequate for testing most applications.

Temperature Cycle

Another factor that affects the total cycle time is the dwell time at temperature extremes. Because the fatigue of solder joints is mainly due to creep, a dwell time is required to allow for stress relaxation. If the dwell time is too short, the number of cycles required to produce a failure will be increased. Fifteen minute dwell times at each temperature extreme is recommended in IPC-SM-785.

Besides shortening cycle time, the test can be accelerated by increasing the temperature swing. A temperature cycle that is often employed is cycling between -55°C and +125°C . However, even if thermal cycling is performed, it is inappropriate to cycle between these extremes if the service environment is within -20°C to +100°C. 9 That's because in the region from about -20 to +20°C, a primarily stress-driven solder response to applied loads at lower temperatures changes to a primarily creep/stress relaxation response at higher temperatures. The damage mechanism, under such conditions, will be different than for more typical use conditions and will probably depend on a combination of creep-fatigue, causing early micro-crack formation which results in faster crack propagation.

Furthermore, if the selected high temperature extreme comes close to the Tg of the laminate material on the PWB substrate, this will have a large impact on the failure mechanisms. '° For this reason, IPC-SM-785 recommends performing thermal cycling from 0°C to +100°C for most use categories. If products will be exposed to temperatures below 0°C and/or above +100°C, the standard recommends adding a number of cycles similar to actual use in number and nature.

For some applications, a smaller temperature variation may be superimposed over a larger one. 14 A fictitious temperature profile for such a case is shown in Figure 3. The impact of a superimposed smaller temperature fluctuation on the overall solder fatigue life must be considered.

For components with sign)ficant heat dissipation, large temperature gradients will be formed inside the components, between the components and the board substrate and within the board substrate. 33'34'35 Therefore, temperature cycling tests are inadequate to provide the required information for components with sign)ficant heat dissipation. For such components, full functional cycling is required, including external temperature cycling and internal power cycling. ^13,36

Figure 3. This is a fictitious temperature profile for a circuit assembly located under-the-hood in a truck.

Vibration Exposure

In some applications, under-the-hood uses, for example, vibration may shorten solder fatigue life. Since assemblies under-the-hood are heated when they are exposed to vibration exposure, except for a short period just after the engine is turned on, exposure to vibration should preferably be performed during the high temperature phase when running a thermal cycling test. Not many laboratories have equipment for this test, however.

Alternatively, thermal cycling and exposure to vibration have to be performed in consecutive tests. Since vibrations mainly affect crack propagation, the test should start with the thermal cycling test, or even better, thermal cycling and exposure to vibration performed alternatively.

Interconnection Failures Inside Packages-Failure Mechanisms

Conventional leaded plastic packages usually have a leadframe that stiffens the package; furthermore, the package is molded in hard epoxy resins. Most of the stresses due to CTE mismatches between package and PWB substrate are taken up by the leads.

Many types of CSPs have a much more heterogeneous buildup and utilize new technologies for making the interconnections inside the packages. Most CSPs have an area array distribution of the interconnection sites and no leads. Stresses due to CTE mismatch between package and substrate will be directly induced into the packages. Hence, an increased risk for interconnect failures within packages can be expected for many CSPs, especially for those with sign)ficant heat dissipation.³⁵

Interconnection failures can, for example, be caused by ripping off solder lands on the interposer substrate, cracking of conductors or via holes on the interposer substrate or by connections breaking between the chip and interposer substrate.

The most extreme stresses that a CSP will be exposed to will occur during soldering of the package, not due simply to the stresses caused by the CTE mismatch. Most polymeric materials absorb humidity. When packages are rapidly heated during the soldering process, high water vapor pressure may build up inside the package resulting in delamination, cracking and swelling. This is often referred to as "popcorning."

Severe popcorning may destroy internal interconnections immediately or cause chip cracking. Less severe cracking may cause microcracks that threaten the longterm reliability of the package. 37 The construction of many CSPs results in the polymeric materials used for their production quickly absorbing water from humid operating environments. Consequently, these packages, as well as many BGAs, are more susceptible to popcorning than conventional plastic packages.

The susceptibility of packages toward internal interconnect failures is, usually by tradition, evaluated according to MIL-STD-883D.

Accelerated Test Methods

The susceptibility of packages towards internal interconnect failures is, usually by tradition, evaluated according to MILSTD-883D. 3 This standard indicates that the impact of temperature variations be tested according to six conditions (see Table 2). The test is a dual chamber test, i.e., the test vehicles are transferred between two chambers of different temperature during the test. The total transfer time between the two chambers may not exceed one minute. This test is, by definition, a thermal shock test.

Although this test has been designed for evaluating the reliability at the device level, it is often also used for evaluating the reliability of the components at board level. (The inadequacy of thermal shock tests for evaluating solder joint attachment reliability has already been discussed).

There are also reasons for questioning the relevance of this test for reliability evaluations at the device level. The fast changes in temperature will cause stress levels inside the package that will not occur in field conditions. Even though the heating of components due to high power dissipation can be very fast, the distribution of the stresses inside the packages will be completely different.

Perhaps more importantly, the stresses in a package soldered to a substrate may be very different from the stresses in a nonsoldered package. For the older type of package with leadframe and peripheral leads providing compliance, this was not a major concern.

Because stresses caused by CTE mismatches between the package and PWB substrate are directly induced into area array components, adequate testing for the reliability of interconnections inside packages must be performed on packages soldered to printed boards.

Another reason that soldered packages should be used is because of the impact the soldering process may have on package integrity. Since the amount of absorbed water will determine the detrimental effect of a soldering process, packages should be preconditioned according to the level to which they have been qualified. Both IPC 33 and JEDEC 39 class)fications are based on six levels.

Since the failure mechanisms will vary for different CSPs and application areas, and due to the limited data available for this type of testing, it is impossible to offer definitive instructions on how to perform relevant testing for interconnection failures inside packages. However, the testing method employed to assess solder joint cracking will probably be aufficient, in most cases.

Corrosion of Metallization at the Chip Surface-Failure Mechanisms

Since all polymers are permeable to moisture, water diffusing into the package may cause electrochemical migration and the corrosion of bond wires and chip metallization. 40 For packages that will be used in harsh environments, corrosion due to gaseous pollution may become a problem.

Corrosion due to water has been _ problem for conventional plastic packages, as well as CSPs. However, field data for more recently produced plastic components with leadframes, such as dual-in-line packages (DIPs), plastic leaded chip carriers (PLCCs) and quad flat packs (QFPs) reveal that they are reliable for most applications.^41,42

Diminishing circuitry sizes and decreasing package thicknesses increase the risk for corrosion damage due to water and corrosive gases diffusing into the package. In addition, the materials used and the build-up of many CSPs make them more vulnerable than conventional plastic packages. Silicone materials, especially, are known to have a high permeability to most gaseous molecules.⁴³

Corrosion Failures

Moisture induced corrosion failures are often tested using a Highly Accelerated Stress Test (HAST), such as the one described in EIA/JESD-22-A110-A. 44 One should be aware, however, that the failure mechanism may be different at the temperatures used in HAST compared to tests performed at lower temperatures. For example, a test performed by McGarvey shows that the failure mechanism shifted from threshold voltage shift at 121°C/1000% RH to a corrosioncaused resistance change at 85°C/85 % RH.⁴⁵

There is no standardized method for assessing the impact of corrosive gases on the reliability of packages. Until that is available, a feasible alternative is to employ some of the mixed flowing gas test methods ("Battelle tests") developed for evaluating the corrosion of electrical contacts.⁴⁶

In many cases, functional components can be used as test components and may even be the best alternative since all functions on a chip may then be tested. In other cases, however, it may be more appropriate to use standardized test chips with double- or triple-track corrosion patterns to achieve a continuous record of changes in electrical performance.^47,48

Whatever type of test package used, it is important for the test components to pass through the normal soldering processes prior to the test, since popcorning will affect the protection against corrosion. In fact, corrosion testing may be the best way to detect minute damage due to popcorning.⁴⁷

CSP Impact

The very great variations in the technologies used for constructing chip-scale packages make it impossible to handle CSPs as a homogenous group when discussing reliability aspects. Furthermore, since many of the technologies used are newly developed and unproven, one can expect new types of failure mechanisms to arise for many of the package types. Therefore, an understanding of the package structure is important.⁴⁹

For most applications, the major reason for reliability failures at the board level is the large difference in the CTE between the silicon chip and PWB substrates. As mentioned earlier, leaded packages have much better resistance against fatigue, due to the compliance afforded by the leads. There are a few CSPs with leads. These can, therefore, be expected to offer good reliability even without the use of underfill. Hitachi Cable's LOC-CSP is one example.⁵⁰

Many CSPs have a ceramic interposer on which the chip is mounted. Since ceramic materials have CTEs similar to silicon, the stresses on the electrical connections between the chip and the interposer caused by temperature changes can be expected to be small. Furthermore, the rigidity of a ceramic interposer will prevent stresses due to CTE differences between package and PWB substrates being distributed into the package.

If the package is mounted on ceramic printed boards, these CTE differences and, consequently, the strain on the solder joints will be small. When organic PWBs are used, which are the only alternative for most applications for cost reasons, the large difference in CTE between the package and the board will create large stresses in the solder joints when exposed to temperature changes.

It may be possible to achieve acceptable reliability without the use of underfill for PWB assemblies that will be used in benign conditions, when expected service life is not too long and when the package is very small. For larger packages and for assemblies that will be exposed to more severe conditions, use of an underfill may be necessary to improve reliability.

Many CSPs have an organic interposer. This interposer will offer some flexibility, resulting in better reliability of solder joints to PWBs compared to packages using ceramic interposers. On the other hand, since stresses due to CTE differences between package and PWB substrates will, to some extent, be distributed into the package, an increased risk for connection failures inside the package is present. Since high stand-off of the packages is very advantageous for reliability, packages with solder balls can be expected to provide considerably greater reliability than packages with solder lands, both when using ceramic and organic inerterposers.

To reduce the stress on the PWB's solder joints, some packages are constructed with a compliant layer. The leading example of this package type is Tessera's BGA ® package. 51 Chip Scale Inc.'s Micro SMT@, package S2 and EPIC technologies' EPIC� CSP 53 can also employ a compliant layer. This compliance will result in low stress levels to the solder joints, making the use of underfill unnecessary, even in rather harsh conditions. The tradeoff, however, is in increased movements in the compliant layer that may lead to increased risk of failures.

Test Vehicles

Test vehicles should be representative of production processes, PWB substrates and normal changes due to ageing, to adequately reflect true conditions. 9 The build-up and thickness of the PWB substrate will sign)ficantly impact the stresses introduced to CSPs.

Furthermore, CSPs with large I/O counts will require new types of high-density PWBs. With new package types, new constructions of PWBs are likely to show altered failure modes. For example, microvia boards with staggered vies and via-inpad display very different build-up and properties compared to conventional FR-4 boards. The reliability of these boards must also be considered when evaluating CSPs that will require highdensity boards. The PWBs cannot be evaluated separately, since�to a large extent�they will be affected by mounted components.

Consequently, adequate reliability testing of packages must be performed on packages assembled on the same type of PWBs that will be used in the final product. Electrical monitoring of the integrity of interconnections must include internal as well as external connections, i.e. the daisy chain must pass through solder joints between packages and printed board and through internal connections via the chip surface.

Packages with significant heat dissipation should have test chips with resistive heaters to achieve power cycling. Packages that will be used in harsh environments should, preferably, have test chips with a corrosion test pattern.

References

1. M. G. Pecht, "Criteria for the Assessment of Reliability Models," IEEE Trans. Comp., Packag., Manufact. Technol - Part B, Vol. 20, No. 3, 1997, pp. 229-234.
2. K. Newman and M. Yuan, "Surface Mount Assessment and Second-Level Reliability Evaluation of Various Chip-Scale Package Constructions," Proc. Pan Pacific Microelectronics Symposium, 1998, pp.lO3-114.
3. U.S. Department of Defense, Test Methods and Procedures for Microelectronics, MIL-STD-8S3D, November 1991.
4. Joint Electron Device Engineering Council (JEDEC), Standard No. 22 (Collection of Test Methods).
5. S. Greathouse, "Chip-Scale Package Solutions--The Pros and Cons," Proc. 2nd International Conf on Chip-Scale Packaging (CHIPCON), 1997, pp.1-9.
6. JEDEC, Stress-TestDriven Qualification of Integrated Circuits, JESD47, July 1995.
7. U.S. Department of Defense, Standard Requirementsfor Soldered Electrical and Electronic Assemblies, MIL-STD-2000A, February 1991.
8. IPC, "Big Changes in DoD Soldering Activities: MIL-STD-2000 Cancelled," IPC Review, Vol. 36, No.4, 1995, p.7.
9. IPC, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments, IPC-SM-785, November 1992.
10. J. Glazer, "Reliability of Printed Circuit Assemblies," C. E Coombs (Ed.), Printed Circuits Handbook, Fourth Edition, McGraw-Hill, 1995, Chapter 37.
11. R-E. Tegehall, "Reliability Verification of Printed Board Assemblies: A Critical Review of Test Methods and Future Test Strategy," Proc. Surface Mount International, 1998, pp.359-382.
12. JEDEC, Failure-Mechanism-Driven Reliability Qualification of Silicon Devices, Standard No.34, March 1993.
13. IPC, Implementation of Flip Chip and Chip-Scale Technology, J-STD-012, January 1996.
14 P. Carlsson, R. Rorgren and P-E. Tegehall, "Tailoring of Test Programme for Evaluating the Reliability of Plastic Ball Grid Array Packages in Automotive Environments," Proc. SEMICON/Europa 96, Geneva, March 27, 1996.
15. J. H. Lau, Solder loins Reliability - Theory and Applications, Van Nostrand Reinhold, New York, 1991.
16. J. S. Hwang, Ball Grid Array ~ Fine Pitch Peripheral Interconnections, Electrochemical Publications Ltd., United Kingdom, 1995.
17. Lau et al., "Solder Joint Reliability of Large Plastic Ball Grid Array Assemblies Under Bending, Twisting, and Vibration Conditions," Circuit World, Vol. 22, No.1, 1995, pp.27-32.
18. M. Nylen, B. Hutchinsson and U. Gustavsson, "Microstructural Degradation of Solder," Proc. Micro Materials 1997, pp.890-895.
19. M. S. Cole, E. J. Kastberg and G. B. Martin, "Shock and Vibration Limits for CBGA and CCGA," Proc. Surface Mount International 1996, pp.89-94.
20. S. C. Bolton, A. J. Mawer and E. Mammo, "Influence of Plastic Ball Grid Array Design/Materials Upon Solder Joint Reliability, The International lournal of Microcircuits and electronic Packaging,Vol. 18, No.2, 1995, pp.109-120.
21. D. R. Banks and R. D. Gerke, "Assembly and Reliability of Ceramic Column Grid Array," Proc Surface Mount International, 1994, pp.271-276.
22. Banks et al., "Reliability Comparison of Two Metallurgies for Ceramic Ball Grid Array, " IEEE Trans. Comp., Packag., Manufact. Technol.- Part B, Vol. 18, No.1, 1995, pp.53-57.
23. Banks et al., "The Effect of Solder Joint Voiding on Plastic Ball Grid Array Reliability," Proc. Surface Mount International, 1996, pp.121-126.
24. A. Mawer, D. Cho and R. Darveaux, "The Effect of PBG Solder Pad Geometry on Solder Joint Reliability," Proc Surface Mount International, 1996, pp.127-135.
25. R. Rorgren, R-E. Tegehall, and R Carlsson, "Reliability of Ball Grid Array Packages in an Automotive Environment," Proc. Surface Mount International, 1997, pp.85-92.
26. E. Bradley and K. Banerji, "Effect of PCB Finish on the Reliability and Wettability of Ball Grid Array Packages," Proc. 45th Electronic Components Technology Conf, 1995, pp. 1028-1038.
27. V. F. Hribar, J. L. Bauer and T. R O'Donnell, "Microstructure of Electroless Nickel-Solder Interactions," Proc. of the 3rd International SAMPE Electronics Conference, 1989, pp.1187-1199.
28. D. R. Frear, E M. Hosking and R T. Vianco, "Mechanical Behaviour of Solder Joint Interfacial Intermetallics," Proc. of the Materials Development in Microelectronics Packaging Conference, 1991, pp.229-240.
29. D. W. Finley et al., "Assessment of Nickel-Palladium Finished Components for Surface Mount Assembly Applications," Proc. Surface Mount International, 1995, pp. 941-953.
30. R. Dudek et al., "An Efficient Approach to Predict Solder Fatigue Life and its Application to SM and Area Array Components," Proc The 47th Electronic Components and Technology Conference, 1997, pp.462-471.
31. M. Bevan, "Effect of Conformal Coating on the Reliability of LCCC Solder Joints Exposed to Thermal Cycling," Proc Surface Mount International, 1991, pp.737-744.
32. H.-M. Tong et al., "Effects of Parylene Coating on the Thermal Fatigue Life of Solder Joints in Ceramic Packages," IEEE Trans. Comp. Hybrids Manuf Techn., Vol. 16, No.5,1993, pp.571-576.
33. R. Darveaux and A. Mawer, "Thermal and Power Cycling Limits of Plastic Ball Grid Array (PBGA) Assemblies," Proc. Surface Mount International, 1995, pp.315-326.
34. H.-J. Albrecht and J. Gamalski, "Fatigue Properties of BGA Solder Joints: A Comparison of Thermal and Power Cycle Tests," Proc Surface Mount International, 1996, pp. 61-80.
35. K. T. Knadle, J. S. Perkins and J. A. Potenza, "Verifying a TBGA Card Assembly Process Using Innovative Reliability Tests and DOE," Proc Surface Mount International, 1995, pp.402-410.
36. W. Engelmaier, "BGA and CGA Solder Attachments: Results of LowAcceleration Reliability Test and Analysis," Soldering eF Surface Mount Technology, No.24, 1996, pp.25-31.
37. R. Gannamani and M. Pecht, "An Experimental Study of Popcorning in Plastic Encapsulated Microcircuits," IEEE Trans. Comp., Packag., Manufact Technol - Part A, Vol. 19, No.2, 1996, pp. 194-201.
37. IPC, Procedures for Characterizing and Handling Moisture/Reflow Sensitive ICs, IPC-SM-786A, January 1995.
39. JEDEC, Moisture-lnduced Stress Sensitivity for Plastic Surface Mount Devices, Standard No.22-A112-A, November 1995.
40. M. Pecht, "A Model for Moisture Induced Corrosion Failures in Microelectronics Packages," IEEE Trans. Comp. Hybrids Manuf Techn., Vol. 13, No.2, 1990, pp.383-389.
41. M. G. Pecht, R. Agarwal and D. Quarry, "Plastic Packaged Microcircuits: Quality, Reliability, and Cost Issues," IEEE Trans. Reliability, Vol. 42, No. 4, 1993, pp.513-517.
42. E. B. Hakim et al., "Plastic-Encapsulated Microcircuits (PEMs): Longterm Dormancy Studies," Circuit World, Vol. 23, No. 4, 1997, pp.26-29.
43. M.L. Minges, Editor, Electronic Materials Handbook, Vol. I (Packaging), ASM International, 1989, p.773.
44. EIA/JEDEC, Highly-Accelerated Temperature and Humidity Stress Test (HAST), Standard No. 22-A 110-A, April 1997.
45. W. McGarvey, "Autoclave vs 85°C/85 % RH Testing - A Comparison," Proc IEEE Int Rel. Physics Symp.,1979, pp.136- 142.
46. W. H. Abbott, "The Development and Performance Characteristics of Mixed Flowing Gas Test Environment," IEEE Trans. Comp. Hybrids Manuf Techn., Vol. l l' No.1, 1988, pp.22-35.
47. O. Selig, R Alpern, and R. Tilgner, "Corrosion in Plastic Packages-Sensitive Initial Delamination Recognition," IEEE Trans. Comp., Packag., Manufact. Technol. - Part B, Vol.18, No.2, 1995, pp.353-357.
48. J. S. Osenbach and J. L. Zell, "Corrosion of Thin Film Aluminum Metallization: Conformal Coating Materials," IEEE Trans. Comp. Hybrids Manuf Techn., Vol. 16, No.3,1993, pp.350-359.
49. V. Solberg, "Qualification Test Planning for CSP," Chip Scale Review, Vol. 1, No.1, May 1997, pp.34-35.
50. G. Murakami, "CSP with LOC Technology," Proc. ISHM '96, pp.594-599.
51. T. Di Stefano, "The BGA as a Chip-Size Package," Proc NEPCON West, 1995, pp 327-333.
52. J. L. Young, "Chip-Scale Packaging Provides Known Good Die," Proc NEPCON West, 1995, pp.52-62.
53. J. E. Kohl et al., "Assembly and Reliability Methods," Proc. Chip Scale International '98, Day 1, pp.129-134.

Dr. Tegehall is a Project Manager at IVF, the Swedish Institute of Production Engineering Research. He holds a Ph.D. in inorganic chemistry from Chalmers University of Technology, Gothenburg, Sweden. Prior to joining the Institute, he worked at Ericsson Microwave Systems on inorganic surface treatments and corrosion problems of electronic assemblies. Readers may contact him at pererik.tegehall@ivfse or 46.31.706.60.00.

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