Flip-Chip and Chip-Scale Package Reliability Modeling

Establishing solder joint reliability requires highly accurate computer models which can predict test failures at field conditions.

-By Dr. Jean-Paul Clech, EPSI Inc., Montclair, N.J.

Figure 1. FC/CSP solder joints are one to two orders of magnitude smaller than BGA joints in volume.

Flip chip and CSP solder joints have smaller load bearing or crack propagation areas than conventional assemblies, implying higher stresses and shorter crack propagation times.

Figure 2. Schematic of underfilled flip-chip assembly

For identical chips in flip chip/CSP or BGA formats, the joint height ratio implies that shear strains in flip chip/CSP solder joints are perhaps 6.25 times higher than in BGA assemblies. Using a Coffin-Manson relationship for solder joint life estimates, the strain ratio results in a fatigue life ratio of about 40.

Figure 3. Shear Strain distribution in underfill layer of silicon-on-ceramic test vehicle (DT= -80°C).

With a volume ratio of over two orders of magnitude, the energy absorbing capability of flip-chip/CSP solder joints is much less than for BGA joints. While solder joint modeling is essential for upfront reliability assessment and for extrapolating test results to field conditions, model verification is key to the application of life prediction techniques to new assembly technologies. This paper presents the validation of the Solder Reliability Solutions (SRS) model for flip chip and CSP assemblies.

Underfilled Flip-Chip Reliability

The thermal expansion mismatch between die and substrate in underfilled flip-chip assemblies (Figure 2) is taken up by the solder joints and the underfill layer, thus providing for solder joint strain relief. However, the mechanical coupling provided by the underfill layer stiffens the assembly. Die stresses increase, and underfilled flip-chip assemblies are sensitive to die cracking. Interfacial stresses between the underfill layer and the die or the substrate lead to a third potential failure mode, underfill delamination.

Figure 4. Predicted and measured die stresses in Sandia's test vehicle (data after 6).

A simplified mechanical model that accounts for bending of the assembly and shear of the underfill layer has been developed.4 The model provides insight into the effects of geometry and material properties on underfilled flip-chip package reliability. The main results of the model validation process follow.

Underfill Shear Strain Data

Figure 3 shows measured and predicted shear strains in the underfill layer of a silicon on ceramic assembly5 subject to a temperature swing AT=-80°C. Measurements are shown as triangles. The predicted shear strain distribution is plotted for several values of the underfill Young's modulus, Eu.

In the high strain region near the chip edge, the model fits best for Eu = 1.4 Mpsi. Sources of discrepancy include model simplifications, the temperature dependence of underfill properties and the absence of end fillets in the model. Maximum shear stresses derived from the model serve as an indicator of delamination risk.

Figure 5. Correlation of solder joint failure data for conventional SMT (shown as diamonds) and underfilled DCA assemblies (shown as squares)

Die Stress Data

Figure 4 shows profiles of predicted stresses on the flip-chip side of a test die6 after cooling the assembly from 160°C to 20°C. Given the scatter of the data, predicted stresses are in good agreement with the measurements. Predictions are slightly higher because the flip-chip model does not account for the lower modulus of the underfill material at elevated temperatures. The maximum die stress is at the center of the die. The stress profile is flat over a large portion of the die, which implies that die integrity is sensitive to surface defects over most of the die.

Correlation of Solder Joint Fatigue Data

Figure 5 shows the SRS correlation of solder joint failure data, i.e., characteristic life (æ^JOINT (cycles)) scaled for the solder crack area (A (in2)) versus cyclic inelastic strain energy (AW (lb.in/in³ or psi)). (Refer to² for information on the SRS model.) The original correlation of fatigue data is for conventional SMT, including leadless and leaded assemblies, and PBGAs. Figure 5 also shows a similar correlation for DCA or underfilled flip chip. The 13 DCA failures⁷ are for assemblies with and without underfill, different joint heights, several underfill and substrate materials.

Figure 6. Correlation of conventional SMT and flip-chip failure data; Horizontal axis is the cyclic inelastic strain energy. Vertical axis is cycles-to-failure, scaled for the solder crack area, times a volume correction factor.

The centerline correlations for conventional SMT and DCA both have slopes close to -1, consistent with existing strain energy models for SMT reliability. ^2,8-9 The DCA data is offset upwards by a large factor. This offset possibly relates to the much smaller size of DCA solder joints, a well-known effect in metal fatigue. The DCA joints, which are smaller than conventional SMT joints, contain relatively few grains and thus have fewer "flaws" or sites for grain boundary sliding and crack growth.

In the mechanical testing of metals, small volume specimens have an improved fatigue life over larger specimens because of the smaller number of flaws or crack initiation sites in a smaller volume of material.

The failure data for conventional SMT and flip-chip solder joints in Figure 5 are brought together in Figure 6 by means of a solder volume correction factor. That is, the correlation in Figure 6 is similar to the original SRS correlation, but with an added volume correction factor on the vertical axis.

Figure 7. Schematic of µBGA on a circuit board.

The correlation is for 51 datasets, 38 of which are conventional SMT plus 13 flip-chip datasets from.⁷ The correlation coefficient for the data in Figure 6 is 0.95. Spread of the data around the centerline is a factor of 2-3x which is typical of fatigue. The introduction of a volume correction factor is motivated by the large effect of specimen volume on fatigue lives. The data in Figure 6 covers a wide range of solder volume, including solder joints of LCCs, SOTs, QFPs, TSOPs, BGAs and underfilled flip chip, that is, the correlation applies to a spectrum of components and evolving technologies. As in previous solder fatigue models^,1,8-9 the strain energy correlation in Figure 6 has a slope close to -1. Finally, the volume exponent on the vertical axis agrees with similar exponents for steel alloys.

Figure 7 is a schematic of a µBGA on a circuit board. The package's most distinctive feature is a low modulus compliant elastomer layer that decouples the die from the flex tape.^10-11 " During thermal cycling, the compliant elastomer layer with low Young's modulus is essentially in shear due to the CTE mismatch between die and tape. With an elastomer that is compliant enough, the solder joints only see the CTE mismatch between tape and board.

Figure 8. The µBGA package's effective CTE and assembly stiffness as a function of elastomer layer thickness is shown.

Effective CTE of the µBGA Package

Using existing theories of adhesive layers solves for stresses and strains in the BAG package. The effective package CTE that is seen by the solder joints is derived from strains on the bottom side of the package.

The model was applied to a µBGA package mounted on 0.062" FR-4 and which contained a 15-mil thick die. Figure 8 shows the effective package CTE and assembly stiffness as a function of thickness of the elastomer layer. The package CTE increases and the assembly stiffness decreases as the elastomer thickness increases. The compliant layer has to be thick enough to provide an effective CTE that is close to that of FR-4. For a thickness of 6 mil, the effective CTE is in the range 15.7 ppm/°C (10 mm die) to 14.5 ppm/°C (15 mm die). Beyond 6 mils, incremental gains in CTE and assembly compliance are limited. The above CTEs are in agreement with a measured CTE of 14 ppm/°C for a µBGA package with 6 mil elastomer.¹²

Thermal Cycling

Thermal cycling solder joint failure data were published ^13,14 for packages similar to the µBGA format, but with a higher modulus material instead of the soft elastomer layer. Thermal cycling conditions were 0°C to 100°C with 15 minute dwells at the temperature extremes. Typical characteristic lives for several board pad diameters (10-16 mil) and standoff heights (13-16 mil) were in the range of 1000-2000 cycles.

Figure 9. Fit of solder joint failure data for µBGA type packages to the correlation band of the SRS model. The µBGA data points are shown as dark solid triangles.

Results are shown in Figure 9 where the µBGA failure data fall within the original correlation band of the SRS model, very close to the model centerline. We plan to further validate the model for µBGA assemblies when additional test results become available.

Figure 10 is a schematic of a ceramic CSP with design parameters from.^15,16 The package can be thought of as a shrunken Ceramic Ball Grid Array (CBGA). Ceramic CSPs with 116 and 220 I/Os were assembled on FR-4 using eutectic paste or solder balls and paste. Test conditions were thermal cycling between -40°C and 125°C with 20 minute dwells at the extremes. For the 220 I/O CSPs assembled with paste only, first failures occurred at about 500 cycles. For the 220 I/O CSP assemblies with solder balls, and thus a higher standoff, first failures occurred at about 900 cycles. Readers are referred to^15,16 for more information on the ceramic CSP experiments.

Figure 10. Schematic of 220 I/O ceramic CSP mounted on FR-4 board.

The ceramic CSP substrate is 0.4 mm thick. Accelerated testing suggests that CBGA assemblies with 1 mm substrates have a fatigue life 2.5 times longer than for CBGA assemblies with a 2.9 mm substrate.¹⁷ This life improvement is attributed to the greater flexibility of thin CBGAs. The ceramic CSP, with an even thinner substrate, flexes during thermal cycling. That is, the thin alumina substrate provides compliancy to the assembly.

For modeling purposes, the ceramic CSP is treated as a multilayer structure with layers of alumina, underfill and silicon that can stretch and bend. Using a multi-layer model that was developed and validated for PBGAs,² we estimate the effective CTE at the bottom of the ceramic CSP as well as the stiffness of the assembly.

Validation of Ceramic CSP Reliability Model

Test results are plotted on the original SRS correlation band in Figure 11. The ceramic CSP data are shown as dark solid triangles, one for a 116 I/O CSP and the other three for 220 I/O CSP assemblies with different standoffs. The four data points fall within the model correlation band. An even better fit is achieved by adding the solder volume effects.

Figure 11. The fit of ceramic CSP failure data to the original SRS model correlation band.

The ceramic CSP test results are plotted in Figure 12, which includes the solder volume correction factor on the vertical axis of the fatigue life correlation. The data lines up almost parallel to the model centerline. The better fit of the data for ceramic CSPs with different solder joint sizes gives further support to the use of a solder volume correction factor.

The Bottom Leaded Plastic (BLP) package is a thin molded CSP with an internal structure reminiscent of thin small outline packages (TSOPs), but with a smaller footprint and without external leads. A schematic of the center BLP (C-BLP) package is shown in Figure 13. Following several iterations of material optimization,^18-20 the CTE of the package was increased from 3.6 to 8.6 ppm/°C²¹ to improve attachment reliability.

BLP Assembly Reliability

BLP assemblies have been characterized in detail, and techniques have been suggested for possible reliability improvements.^18-21 One option is to assemble packages on boards that are better CTE-matched to the BLP package.

Figure 12. Fit of ceramic CSP failure data to the SRS correlation band with volume correction factor on the vertical axis is shown.

Figure 14 shows Accelerated Thermal Cycling results (ATC: 0°to 100°C) for 28 I/O BLPs on organic boards with different CTEs. When the board CTE is reduced from 17.3 ppm/C to 13.4 ppm/C, solder joint fatigue life increases by a factor of four. Choi et al.²¹ modeled the board CTE effects using the SRS model. Their life predictions, shown in Figure 14, follow test results accurately, thus validating the model for BLP assemblies.

Conclusions

The SRS solder joint reliability model has been validated for flip-chip assemblies, BGA packages, ceramic CSPs and BLP packages. The existing correlation of solder joint lives has been refined to include a solder volume correction factor which captures the effect of specimen size on the fatigue life of metals.

Figure 13. Schematic of C-BLP package assembly; cross-section is in the short direction of the package.

The extension of the model to flip chip and CSP assemblies can help qualify emerging assembly technologies. The model provides the most value in upfront reliability assessment and is of use to derive acceleration factors. (Note: This is a revised version of a paper presented at Surface Mount International 1998 and is used with the permission of the copyright owner.) Acknowledgement

The author acknowledges Robert Lanzone for providing design parameters for the ceramic CSP experiments.

Figure 14. The effect of board CTE on the reliability of 281/0 BLP assemblies. Test results and modeling are by Choi et al.21

References

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Dr. Clech is the owner of EPSI Inc., where he developed the SRS model and application software. He received a degree in materials science from the Ecole Centrale de Paris, and a master's and Ph.D. in mechanical engineeringfrom Northwestern University. He consultsfor and has given SMT reliability training at institutions in Asia, Europe and North America. Readers may contact him at jpclech@aol.com, 973.746.3796, fax 973.655.0815.