November - December 1999
eMail the Editor
Chip Stacking Offers Space Savings with Small Investment
- By Robert CrowleyContributing Editor
The miniaturization trend in portable products is relentless. While there are natural limits on the minimum useful size of hand-oper-ated devices containing keypads and displays, the drive to reduce the size and mass of the PC assembly continues.Two well-established miniaturization solutions are silicon integration to reduce the number of components and 告p-chip assembly to increase the assembly density.
Space Savings, Small Investment
A third solution, the stacked-chip package (see the illustration), has become established in the cellular handset industry. Many companies have started using stacked-chip technologies to gain immediate space savings with minimal investment in new silicon designs or SMT assembly processes.
Three-dimensional electronics assembly is not new, but its use in mainstream electronics manufacturing has been limited. The complexity of stacking chips, packages or modules has limited 3-D packaging to low-volume specialized applications such as military electronics, high-speed computers and implantable medical devices.
While it is possible to build an entire system using 3-D stacking technology, the biggest stacking trend today is a simple approach with two chips in one package. This simple stacking technique is often referred to as 2.5-D packaging, because it is smaller than traditional 2-D PC board assem-bly but not as complex as 3-D assembly which employs vertical electrical buses.
Chip stacking inside a TSOP has been in production since 1995. In this instance chips are mounted on both sides of a leadframe die-attach pad. One chip is face-up in the package and the other is face-down. The chips are wire bonded to the leadframe on each side. This technique works best with the same memory chips (DRAMs for example), with one chip processed as a mirror-image of the other to simplify wire bonding.
Flexible Substrate
|
| The stacked chip package has become commonplace for cellular handsets. |
In the CSP world, many companies are making stacked-chip packages with SRAM and 吧sh memory stacked one atop another on a single side of a rigid or 呈xible substrate. Both chips are wire- bonded to the top of the substrate and encapsulated by overmolding. Solder balls on the bottom of the substrate complete the package. Sharp began stacked CSP production in May 1998, and Intel announced a stacked CSP in May 1999.
More sophisticated stacking structures are in development. An interesting approach to watch is based on a combination of wire bonding and 告p-chip. Two structures may be assembled on one side of a substrate. An IC can be mounted by 告p-chip on the substrate, followed by mounting a wire-bonded die on the back side of the 告p-chip. Conversely, a wire-bonded die could be attached to the substrate with a 告p-chip die mounted to the face of the wire-bonded die. The wire-bonded die requires a redistribution layer to create land pads for the second chip.
Chip-stacking in a chip-size package provides a 40 percent reduction in board area without requiring new assembly processes.
The IC packaging world is not headed towards consolidation into fewer package styles; in fact an increasing number of application-specific packages are being developed that are optimized for the cost and performance requirements of a specific type of product.
Stacking chips inside a chip-scale package is just another example of this trend and an excellent way to save board area for portable products.
Mr. Crowley is president of Redpoint Research, a technology analysis and consulting company in the microelectronics packaging field. He can be reached at crowley@redpointresearch.com.