November - December 1999
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BIST on CSPs Enables Massively Parallel Testing
- By Paul M. Sakamoto Contributing Editor
Built-In Self-Test (BIST), as it relates to IC design, is the use of on-chip circuits to guarantee the function of the IC without the use of a complete external testing resource, such as component automatic test equipment (ATE). BIST is not a new concept; in fact it has been around almost since the beginning of the industry, although its widespread adoption has been slow due to several factors.
- BIST circuitry takes up valuable real estate with functions that have minimal or no value to the end customer. Therefore, the inclusion of BIST may have trouble paying for itself in many applications.
- Aggressive price-to-performance improvements in ATE have reduced the attractiveness of many BIST implementations.
- BIST circuits can fail just like application circuits, leaving at least an emotional need to provide external reference testing.
- BIST circuits occupy design and layout time just like application circuits, impacting time-to-market and engineering capacity goals.
Generally chip-scale and near chip-scale-packaging processes hold a number of units in a frame or panel of devices that are handled in parallel through most of the process after die bonding and/or encapsulation. The resulting assembly of units in batch mode can be handled faster than individual units can be assembled.
Moreover, if the devices can be electrically isolated while still held together, the testing can also be done as a unit. Memory devices, particularly DRAMs, have been tested as individual units in parallel for years.
DRAM Testing
The very long test times of DRAMs, in the minute-to-minutes range, overcome the handling time of indexing from 16 to 128 units at a time, in a parallel handling/testing work-cell. This handling time can be on the order of 10 or more seconds, depending on the package, devices in parallel, and the handling equipment involved. Still as long as the test time for a single unit exceeds the handler index time, preferably by a factor of two or more, parallel testing makes sense.
Many non memory applications have a reverse ratio of test to handling time. For instance, many microcontrollers have sub-second test times. For these devices, the test time is so fast that the index times of highly parallel handling equipment cause the expensive ATE to sit idle for most of the cycle. In addition, many logic and mixed signal devices have such a high pin count that the number of devices in parallel is limited by the available channel count in the ATE. The team of chip-scale processing and BIST can overcome these two issues.
Device Handling
Strip, panel or matrix handling, as used in the chip-scale process eliminates the indexing time associated with discrete device handling. Careful BIST implementation can eliminate the need for a high pin count tester at the longest test steps. This is especially true of long embedded memory tests. Although there are a lot of reasons why parallel test on the order of DRAM test is unlikely to be occurring soon, doubling current logic and mixed signal test densities should be possible immediately.
Finally, cell-based design tools and BIST vendors of embedded memory, logic and even analog have greatly reduced the design time per application, as well as the verification time for fault and performance coverage.
It will be interesting to see if chip- scale processing gives BIST the boost that it needs.
Mr. Sakamoto is vice president of the Memory Products Division at Credence Systems Corp., Fremont, Calif. Contact him at paul_sakamoto@credence.com.