November - December 1999
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Chip Maker Atmel Betting on Wafer-Level Die Ball Grid Array
- By Harvey MillerContributing Editor
Atmel, San Jose, announced an innovative drop-in replacement for eight-lead TSOP serial EEPROMs two years ago. That was about long enough to develop an infrastructure and gain market share before competitors emerged. Two customer needs drove its development: - A lower profile for cell phones
- An inability of one leadframe package, with its singular pinout pattern, to accommodate the transitions from 256K to 512K-and then to 1 megabit
Array packages, chiefly BGAs with their organic PC board substrates, have marched to the two billion level in five years, replacing leadframe QFPs in part, and moving to dense lead counts where QFPs dare not go.
Now the new BGAs are making a contribution to the old small outline packages, helping them survive.
Are substrate SOs a trend? Not according to Atmel marketer Scott Avery and Amtel engineer Andy Korats, who are placing their bets on Atmel's Die Ball Grid Array (DBGA) package.
The DBGA is a wafer-level package-magic words these days, and it's one-tenth the size of its counterpart SO! The package employs 0.5 mm solder balls on 0.75 mm pitch and does not require underfill.
Lithography Tools in your Future?
Ultratech Stepper and Tamarack Scientific provide lithography tools for wafer fabrication, but these companies have also joined the packaging world-the finer lines on denser package substrates demand their tools.
Take, for example, IBM Microelec-tronics' High Performance Chip Carrier (HPCC) aimed at high I/Os. The HPCC is a BGA with several unique features, including a PTFE substrate (low K and DF) and 28-micron lines and 50 micron laser-drilled through-vias with a copper-Invar-copper ground plane and stress absorber.
Sound familiar? It reminds me of the W.L. Gore, PTFE Microlam, flip-chip BGA package with its blind and buried microvias. That alone may be an over $40 million business, based on some indirect evidence. We will see IC packages with over 5,000 leads very early in the next century.
That's why wafer bumping offers such bright promise. Flip-chip-on- die technology is going to be of growing importance.
Focus Interconnect in Austin, Texas, backed in part by the Singapore government; Chip Bond in Taiwan, and, of course, Flip Chip Technologies, backed by Delco/Kulicke & Soffa are all taking aim. They may soon be joined by Pac Tech GmbH with San Jose and Berlin locations next year.
Maybe copper metalization replacing aluminum will be another enabler for flip-chip-on-wafer some day by eliminating under-bump metalization. That development also opens the door to copper-wire bonding (which K&S has introduced), spreading the benefits of higher conductivity and lower cost.
But not all solder bumps are mass re§owed on wafer. A new class of wafer-level package has emerged that may be soldered on PC boards. These packages, however, require "large" 13-mil bumps (and over) instead of small, re§owed 4-mil solder bumps. No underfill is needed.
(The larger bumps supposedly absorb the stresses due to the differing TCE between silicon and the PC board.)
Two major competitors, Motorola Manufacturing Systems and Shibuya, believe in wafer-level packages, and both are offering new wafer-level, discrete solder placement machines.
Motorola's entry is of particular significance, both as an internal indicator of package development and as a nod of affirmation of the importance of the market, since other parts of Motorola Semiconductor have been contracting or divesting.
Mr. Miller is editor/publisher of InfraFOCUS, an industry newsletter published in Palo Alto, Calif. Readers may contact him at hmiller560@aol.com or by phone at 650.327.2029.