November - December 1999
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Company News
National's Chip-Size Package Rolled Out for Analog Products
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| National Semiconductor's micro SMD technology has been employed for 13 analog ICs. |
The analog products packaged as micro SMDs include CMOS timers, shunt regulators, op amps, temperature sensors and an audio amp.
National observes that the wafer-level process slashes component size and eliminates several manufacturing steps. One result is a reduction of manufacturing cycle time by two to three weeks.
The company's proprietary encapsulation process, employed on the front and back of the wafer, produces a packageless device. The micro SMD products conform to standard JEDEC pinouts, assuring accurate circuit board placement using existing mounting equipment.
Customers, adds National, "can transition to micro SMD parts without any retooling of standard surface mount equipment."
National claims that the micro SMD technology yields more reliable components, because shorter interconnections result in low inductance and minimal signal degradation. The micro SMD parts also meet JEDEC level-1 specs for moisture sensitivity.
The micro SMD is currently available in 4-, 5- and 8-I/O packages. The 4-bump micro SMD boasts a total surface area of roughly 0.8 mm, which amounts to an 80 percent reduction in footprint over the SC-70, the smallest "traditional" package available.
The 5-bump micro SMD is about 88 percent smaller than the SOT 23-5 package, while the 8-bump micro SMD can provide up to 85 percent savings in board space compared to an 8-lead mini-SOIC. (Key attributes are shown in the table.)
www.national.com
| Key Attributes for Micro-SMD 8 I/O | |
| I/O Count | 8 |
| Pitch | 0.5 mm |
| Outline | 3 x 3 peripheral |
| Package Weight | 0.0038 gm |
| Package Thickness | 0.825 mm - 0.922 mm |
| Package Width | 1.40 mm - 1.45 mm |
| Package Length | 1.40 mm - 1.45 mm |
| Bump Diameter | 0.16 mm - 0.18 mm |
| Bump Height | 0.12 mm - 0.14 mm |
| Bump Coplanarity | ±0.015 mm |
| Shipping Media | Tape & Reel |
| Desiccant Pack | Level 1 |
| (Source: National Semiconductor) | |
Amkor and Sharp Electronics Trade Stacked-Chip Technology
Chandler, Ariz.-Amkor Technology Inc. and Sharp Electronics Inc., Osaka, Japan, have reached an agreement to share stacked-die chip-scale packaging assembly technologies. The agreement licenses Amkor to employ Sharp's tape-based, stacked-chip assembly methods to build stacked chips for Sharp and other device makers.
Sharp, meanwhile, has been lic- ensed to use Amkor's laminate-based ChipArray™ technology to package its products. Both companies currently assembled stacked-chip CSPs using their own technologies.
The agreement also calls for codevelopment efforts aimed at enhan-cing stacked CSP technologies and reducing costs.
"Tape" and "laminate" refer to the substrate on which the die are mounted and wire-bonded.
www.amkor.com
ESEC Sells Zevatech Division
Morrisville, N.C.-The ESEC Group of Cham, Switzerland, has agreed to sell its Zevatech Circuit Board Assembly Division to Juki Automation Systems Inc. (JAS). Gary Burroughs, who was most recently with Speedline Technologies, was appointed president of JAS several months ago when the company was formed here. In its announcement, Tokyo-based Juki management said it "anticipates few changes in Zevatech personnel in both Europe and North America. The company will handle the support and assume the existing warranties of the extensive Zevatech installed base of SMT systems in the marketplace and will offer employment to the majority of the existing Zevatech employees."
www.jas-smt.com
ASAT Ltd. Names Jerry Lee New CEO
Hong Kong-Jerry Lee has been named CEO of ASAT Ltd, a wholly owned subsidiary of QPL International Ltd. He joined the company from SCI Systems, where he was senior vice president. Lee previously served as country managing director of Texas Instruments in Malaysia, was a vice president of Read-Rite International and operated his own consultancy.
www.asat.com
Cookson Forms Greenline, Leadfree Initiative
Franklin, Mass.-The Cookson Electronics Division (CED), which includes Speedline Technologies, has announced the creation of "Greenline," a highly focused, company-wide initiative aimed at offering completely lead-free manufacturing. Cookson says that Greenline is "the centerpiece for CED's sizable, lead-free research efforts, which includes full support of international industry consortia, academia, government and trade associations ƒ" Greenline's capabilities were demonstrated at Productronica in Germany. recently with the assembly of 100 percent lead-free PC boards on a dedicated 30 meter production line.
www.speedline.cookson.com
Chipscale Robotics Wins Coherent Order
Fremont, Calif.-Chipscale Robotics has won an order from Coherent Inc. for the its high accuracy DSH-5000 pick-and-place die stacking system. The system employs both up- and down-looking optics for precision die stacking and inspection. Coherent will use the system in its manufacturing operations. For more information, contact Ron Gilman, rongilman@chipscalerobotics.com.
www.chipscalerobotics.com
Taiwan's Semiconductor Industry Largely Unscathed After September Earthquake
Taipei, Taiwan-The September 20 earthquake that devastated central Taiwan, killing thousands, left the Island's semiconductor industry largely unscathed, according to preliminary reports. With the exception of a quake-caused power outage that impacted wafers at the front-end of some chip makers in Kaosiung, Taiwan's Silicon Valley, IC makers reported no damage to their equipment or facilities.
The UMC Group, Taiwan's largest wafer foundry, reported no damage to its fab buildings or machinery, other than some glass breakage, such as quartz furnace tubes, and the loss of a few ceiling tiles.
"At this time, we anticipate that the earthquake's impact on UMC Group's overall production for the year will be minimal, although we are still assessing the impact to September output," said Jim Kupec, president of UMC Group USA.
John Wu of Orient Semiconductor Electronics, Kaosiung, said assembly and test operations were not affected. Operations at the packaging foundry, added Wu, are proceeding "as usual."
Wu, however, said he thought the Taiwanese chip industry would be impacted negatively over the short term due to a lengthy power outage in the Hsin-Chu Science Park.
Siliconware Will Offer Web-Based Design Services
San Jose-Siliconware USA is claiming an industry first by providing Web-based BGA design services to North American users. The Taiwan-based Siliconware says the design service is the result of a strategic partnership between the packaging foundry and CreoSys Inc. CreoSys supplies the "Package Cruiser" software through its Web site www.creoweb.com.
Customers can browse their BGA design in a stacked- or layer-by-layer format on the Web, and can zoom into individual areas or traces within the layout.
The designs can be viewed simul- taneously by Siliconware's San Jose Technology Design Center and the customer. CreoSys says PackageCruiser eliminates the need for expensive EDA or CAD tools to review complex designs.
www.spilca.com
www.creoweb.com
ON SemiconductorOpens in Slovakia
Piestany, Slovakia-ON Semiconductor, formerly a division of Motorola, has opened a fully refurbished semiconductor production facility here. The com-pany claims to be the world's largest supplier of metal-gate logic ICs. The company is doing business as Slovakia Electronics Industries in the former Tesla Piestany facility, which ON purchased in September.
www.onsemi.com
Wafer-Level Packaging Seen as New Paradigm for Interconnection
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| Rick Short of Indium Corp. of America (left) discusses solders with Gabe Cherian, president of Cherian Enterprises. |
Contributing Editor
September's CSI technical program, presented by SEMI, emphasized that wafer-level packaging will become the new paradigm for interconnect technology in the next century.
Key events included an Executive Briefing on chip-scale and wafer-level Packaging, the Wafer-Level Summit, keynoted by Dr. Rao Tummala of Georgia Tech and the CSI Technical Symposium.
This paradigm shift from CSPs, particularly to those made at the wafer level, will shape the electronics industry by reducing packaging costs and enhancing system integration and interconnect density, according to Dr. Tom Di Stefano, organizer of the Executive Briefing.
Die Shrink
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| Mrs. Silicon Valley (Debra Walker) was on hand at the CSI/SMTA International show with husband Jim Walker of Dataquest. |
Program speaker Mike Campbell of BPA Ltd., noted that wafer-level packaging will be able, additionally, to manage die shrink, and will result in relaxed design rules for packages and substrates.
Vern Solberg of Tessera said that CSPs will play a pivotal role in product miniaturization within the fast-growing wireless market, while wafer-level packaging will dominate the memory packaging market.
Issues Discussed
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| Ed Korczynski of Tru-Si describes the company's wafer-thinning process to show visitors. |
Important issues that emerged from CSP panel discussions at the September 15 program, included:
- The need to reduce the cost of CSPs relative to leaded packages quickly. Unfortunately, patents and intellectual property become bariers to standardization, which is key for cost reductions.
- The definition of a true CSP is tied to such issues as die shrink, package type and die layout.
- An 0.5 mm pitch is not the best solution for OEMs, since most mother board manufacturers can't route signal lines for that pitch.
- Multilayer boards are not good for for 0.5 mm pitch CSPs. They are also costly.
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| Prof. James F. Gibbons, Stanford University, delivered the luncheon keynote talk on "The Relationship Between Stanford University and Silicon Valley." |
With the rapid movement toward further product miniaturization for electronic devices and systems, new opportunities for advanced substrates (boards and §ex) are being created.
Several companies have gone on a capital spending binge to develop HDI boards for portable products. About 50 companies are making HDI boards world-wide, with about 83% of these producers in Japan, according to speaker Solberg.
Unitive Names Lanzone VP of Sales and Marketing
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| More than 800 patents relating to CSPs, BGAs and Wafer-level packages are expected to be filed by yearend. |
Research Triangle Park, N.C.-Unitive Electronics has named Robert Lanzone vice president of sales and marketing, reporting to Wayne Machen, CEO.
Before joining Unitive, Lanzone was general manager of flip-chip packaging for Kyocera America, San Diego, Calif. Earlier, he worked for IBM and Hughes Aircraft.
www.unitive.com
Abpac and STI Announce Custom Enhanced BGAs
Phoenix-Abpac Inc. announced that it can produce custom enhanced BGAs in less than four weeks from design to delivery using Substrate Technology Inc.'s Ultra BGA™ package technology. STI's Ultra BGA is a cavity-down package using sequential build-up construction with plated-through microvias. A single-piece heatsink construction and integrated die cavity is claimed to provide superior thermal performance over the two-piece heatsinks commonly used.
"Using STI's technology, we can provide a very high-performance pack-age with multi-metal interconnects, including grounded heatsinks. These features are ideal for the high-speed marketplace," according to Robert C. Marrs, Abpac president.
The Ultra BGA has passed JEDEC Level III reliability tests, reports STI of Carrollton, Texas. The company says structural reliability has been achieved through the use of high-performance modified epoxy dielectric, minimal mechanical interfaces, rugged plated-through vias and a proven epoxy-based solder mask.
www.abpac.com
www.sti-dallas.com
Chip-Scale and BGA Patents Will Exceed 800 by Yearend
Montara, Calif.-By yearend, more than 800 U.S. patents relating to chip-scale, BGA and wafer-level packages will be on file with the patent office, according to a new report by International Intercon-nection Intelligence. The graph depicts the rapid growth of patents for these new technologies. By the end of 1998, nearly 600 patents were found inolving various aspects of these advanced packaging technologies, according to III. For details, contact III at iii1@ix.netcom.com or phone 650.728.5270.
Allteq Philippines Will Rep Some K&S Products
Fremont, Calif.-Kulicke & Soffa Industries has appointed Allteq Industries Inc., Fremont, its exclusive representative in the Philippines to sell and service several existing product lines. The agreement between K&S of Willow Grove, Pa., and Allteq was effective October 1 and includes the K&S 4500 series of manual wire bonders and the 980 series of semi-automatic dicing saws, wafer mounting systems and wafer washing stations.
Rohm Appoints Sunsil Inc. Its Major Accounts Sales Rep.
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| Seth Alavi |
Prior to forming Sunsil, Alavi was vice president of sales at Tessera, San Jose.
Sunsil's associates include Dr. Vivek Dutta, Cemal Mehmet, Dr. Makoto Shinohara and Dr. Samuel Wang. For more information, e-mail salavi@ix.netcom.com or phone 925.735.3076.
Karl Suss Celebrates 50 Years in Business
Munich, Germany.-Karl Suss, a supplier of semiconductor manufacturing equipment, celebrated its 50th anniversary on September 17. Founded in 1949 by its namesake, the company began operations in a garage. Today the company employs more than 500 worldwide.
OSE Selects RVSI Vanguard
Taiwan's Orient Semiconductor Engineering has selected Vanguard's ball placement equipment for CSPs.
IBM Ships One Million Copper Power PC Chips
Fishkill, N.Y.-IBM has shipped one million copper PowerPC processors, just one year after it began delivering its first copper chip. The company said its copper processors are "fueling the company's growth as a major OEM supplier to networking gear makers." IBM's newest processor, the PowerPC 440 is shown above. (Source: IBM Corp.) www.ibm.com
Equipment Orders
Allteq Industries
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| Model LFI3060 inspection station |
Kulicke & Soffa Industries
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| Model 8020 ball bonder |