CSP Designed to Overcome Lead-on-Chip Limitations

Patent Number:
5,920,118
INVENTOR/Assignee
Hyundai Industries Co., Ltd.
Inventor:
Byoung Sik Kong
Title:
Chip-Size Package Semiconductor This patent describes the construction of a low cost, easily assembled chip-scale package that uses a ceramic substrate for its base.

The approach described in this patent is designed to overcome the limitations encountered in using a typical lead-on-chip (LOC) CSP (Figure 1).

Drawbacks

Figure 1. Figure 1. Typical LOC CSP

One drawback with the design in Figure 1 is the difficulty of molding it. There are opportunities for mold §ash to get on the leads and on the back surface of the IC. Due to the small size, any voiding can expose parts of the chip or interconnect. It is also difficult to change package thickness with this approach.

Another drawback is that when the leads are trimmed close to the package body, damage can be done by chipping the molding or cracking the package.

Still another limitation involves the connections, which are generally limited to a single row on each side of the package. This limitation becomes more important as the number of I/O increases.

Figure 2 shows the basic construction of a CSP that overcomes the drawbacks noted while resulting in a low cost, easily manufactured CSP.

A ceramic substrate with a slot in the center is attached to the IC using two pieces of tape, as shown. The solder balls on the substrate can be applied prior to or after attaching.

The IC pads are connected to metallization traces on the bottom surface of the ceramic substrate by wire bonding.

Package Sealing

Figure 2. Basic construction of a CSP

After assembly the package is sealed using a dispensable encapsulant. It appears that two separate dispensing operations may be required-one from the top and another from the bottom-to encapsulate the slot area.

Both operations should be relatively fast since the encapsulant only needs to §ow a short distance by capillary action. The encapsulation resin is then cured

By using a dispensing process for encapsulation, many of the problems associated with molding a package this small can be eliminated. Dispensing also eliminates an expensive mold die.

This design provides an LOC package that has the same footprint as other CSPs used for memory chips.

An advantage with using a ceramic substrate is that it provides much better thermal properties compared to other types of organic material. These enhanced thermal properties allow the package to offer better heat dissipation.

External connections are made by applying §ux to each pad, placing a solder ball on top of the §ux, and IR heating.

One obvious feature is that there are no vias in this substrate. The metallization pattern is very simple, and manufacturing is accomplished in large arrays, which results in a low cost part. With all of the metallization on one side only, costs are further reduced.

The metallization pattern is formed first by electroless nickel plating and then by protecting the surface with electrolytic gold.

A solder mask is applied over the plating to eliminate shorting between traces. The solder mask covers everything except the solder ball pads and the wire bond area.

The ceramic substrate can be made very thin enabling the overall package thickness to be less than packages using leadframes.

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