An Expert Looks at the Issues™

Dr. Jean-Paul Clech

By definition CSPs have a high silicon content, thus their effective CTE is low and not well matched to the CTE of organic boards. Solder joints have shrunk, compared to conventional SMT assemblies, resulting in less solder volume to take up the component-to-board thermal expansion mismatch or other mechanically induced deformations. The key to second-level reliability is to reduce stres-ses and strains that are applied to the solder joints and ensure that wear-out failures occur past the design life.

The CSP's construction and materials dictate the effective CTE of the package and the compliance of the assembly, two critical parameters for second-level reliability. For CSPs this situation is similar to that of conventional leaded packages where the package contents (die, leadframe, molding compound) determine the expansion of the package, and the lead geometry and leadframe material determine lead compliance.

For example, the elastomer layer of µBGA-type packages provides for decoupling between the die and the polyimide tape of the package, a design that gives compliance to the package and raises its CTE to a level that is comparable to that of FR-4 boards. Other CSPs have a low CTE and very little compliance built-in. Their attachment reliability is limited by the die and package size. Possible improvements can be achieved by optimizing ball and pad diameters.

QHow are CSP suppliers responding to the need for improved reliability?

AFrom the very beginning, solder joint reliability was identified as one of three hurdles to the widespread adoption of CSPs. The other two are cost and infrastructure. Given the impact of package parameters on the final assembly, many package suppliers are responding to the issue proactively, often in synergy with equipment manufacturers or through participation in industry consortia. For example, some suppliers of over-molded CSPs have selected molding compounds that enable raising the effective CTE of their packages. Others offer CSPs with a choice of substrate thickness that is tailored to meet specific reliability requirements. This type of §exibility allows expanding the realm of applications of a given CSP family.

Reliability-conscious organizations are addressing (or have addressed), the solder joint reliability issue by using a combination of accelerated testing and modeling. Reliability modeling provides a head start for initial optimization of package parameters, followed by model verification under accelerated test conditions. Tests must be carried to failure to acquire meaningful failure distributions and identify other potential failure modes. Doing one's reliability homework up front is worth the investment. Suppliers who do it are better equipped to meet their customers' requirements. Reliability may make or break a package and proven attachment reliability is a strong selling point for CSPs.

QCSPs are compared to §ip chip. Two of their advantages are testability and ease-of-assembly. Are CSPs more reliable than §ip chip? Do you need underfill for CSPs? How about new wafer-level packages?

AGiven the variety of CSPs, §ip-chip designs and underfill materials, one cannot make a blanket-statement on the attachment reliability of CSPs versus §ip-chip. Each design has to be evaluated on its own merits with respect to end-use requirements.

An underfill material with a high enough modulus can boost the reliability of §ip-chip solder joints by over one order of magnitude. However, underfilling introduces other potential failure modes. Underfill delamination often is the primary failure mode. Once underfill delamination starts, delamination cracks propagate at a rapid rate and the solder joints fail shortly thereafter. Low §ux residues, cleanliness of the board solder mask and of the die passivation enhance the adhesion strength of underfill materials and are critical to attachment reliability. The third failure mode, die cracking, is sensitive to surface defects and die strength, both of which are supplier- and process-dependent.

Underfilled CSPs may be needed to meet certain reliability requirements similar to underfilled PBGAs in high-reliability applications. Package size is a limiting factor for many Wafer-Level Packages (WLPs) because of inherently low CTEs and stiff constructions. Here again solder volume and pad sizes can be optimized to improve attachment reliability. Underfilling of WLPs is a possibility, and the lessons learned with underfilled flip-chip provide useful guidelines to extend the reliability of WLP assemblies.

QWhy are new test methods, such as mechanical fatigue, drop tests and vibration so popular for CSPs?

ACSPs have made a significant entry into consumer markets with products such as portable telecommunications and computing equipment. The "new" test methods are intended to mimic actual loads which CSP assemblies experience in use.

For example, cyclic board §exing is intended to capture repeated loads that are exerted on the assembly when punching keys on the dial-pad of a cellular telephone. Portable electronics are expected to be dropped quite a few times. Shock and vibrations are a reality during shipping, handling or under any transportation conditions. Thermal cycling remains insidious, but is alive and well for CSP assemblies. Equipment that is left in the compartment or car trunk, or is being carried indoors and outdoors through the seasons, undergoes thousands of thermal cycles.

At this point there are few guidelines or standardized tests for CSP assemblies. Individual companies have designed batteries of tests that best represent the expected use conditions for their own products. This may change in the future thanks to the efforts of industry associations such as the IPC.

For test results to be meaningful-say a board passes 1000 cycles between 0C¹ and 100¹C-designers still bear the responsibility of extrapolating test results to actual product use conditions.

QWhat are the critical issues for PWBs, especially those with microvias?

ASurface finishes need to be looked at carefully in terms of assembly yield, quality and reliability. Small size solder joints are sensitive to intermetallics issues. Thin joints with a high intermetallics content are brittle and may fail catastrophically under a single stress cycle. This needs to be considered up front, when using gold plated surfaces.

The thin walls of microvias (about 1 mil or less), the high expansion of unsupported resin and the possibly large numbers of vias in the built-up layers have revived the problems of copper barrel cracking and copper-to-resin delamination.

Small aspect ratios, thick via plating, uniform and controlled copper thickness, and good adhesion between copper and resin are the keys to microvia reliability.

Excessive board warpage-especially for non symmetrical multilayer stacks-and warpage of CSPs during reflow may also affect assembly yields or lead to early wear-out of poorly shaped solder joints. Board thickness can affect CSP attachment reliability as well. In general, thinner boards provide greater compliance and improved CSP attachment reliability.