New Approaches to Reliable Flexible Interconnections for CSPs

We have developed two different approaches to achieve stress-free interconnections at low cost. One method employs molecularly flexible conductive adhesive as a solder replacement. The other approach (known as Chip-Coupler™ technology*), uses a molecularly flexible dielectric with embedded metallic wiring (of a substantial length) to decouple stress.

Figure 1. Resistance variation of thermoplastic bumps with temperature is shown. (Diamond shape corresponds to control lines without any bumps)

Historically, the main issue with polymer-based bumps has been reliability, especially under temperature cycling and humidity conditions. We prepared several test samples for a thorough reliability evaluation of polymer materials using thermoplastic bump material (LTP8150-IS). The test sample consisted of an upper ceramic (alumina) layer with metallization and pads for subsequent bumping. The lower part is a silicon piece coated with SiO2 and metallized to form a matching pattern to the bumps. (Similar testing based on FR4 substrates will be reported on later.)

The upper layer of the test sample is about 0.3 in. on the side and the lower (Si) layer is about 0.5 in. on the side. Silicon and ceramic as mating substrates were selected as a worst case scenario for this system without underfill, which allowed us to investigate the stress-based effects due to the CTE differences during actual packaging applications.

We formed sockets made of polyimide to facilitate an alignment-free bump insertion technique. A daisy chain of various numbers of bumps was formed in the structure when the two pieces were joined together. The resistance of the daisy chain was measured during tests. (The test sample was wire-bonded in a PGA-type package for automated testing. )

Test Plan

Figure 2. Chip- and wafer-scale packaging or chip-on-board with patented "Hyper-Conductive"

We used a test plan based on modified MIL-STD techniques. The plan had several components: preliminary temperature, temperature storage, temperature cycle, temperature shock, temperature and humidity storage, compression strength, pull strength and shear strength. All samples were subjected to all tests. Additionally, individual control samples were added at each test. Therefore, the results indicated the cumulative changes in the bump resistance and could be considered worst-case deviations.

Temperature Cycle Test

The resistance of each daisy chain on various test samples was measured after the following temperature cycles: -65ÁC to +150ÁC, 500 cycles, 10 min. dwell at each cycle, 10ÁC/min. transitions in air.

The resistance variations for thermoplastic bumps were in the range of ±0.500 ohms. Resistance increased (or decreased) slightly with increasing (decreasing) temperature. The resistance variations of thermoplastic polymer bumps were comparable to the resistance variation of control lines without any bumps.

The error is due mainly to contact resistance changes at the wire bond, connector and board interfaces. We concluded, therefore, that the resistance variation of the bump material was negligible during temperature cycling.

We did not observe the increased resistance leading to temporary open circuits below -30ÁC that was observed on thermoset materials. No failures (open or short circuits) were observed. (A typical bump resistance variation is shown in Figure 1.)

Temperature Storage Test

Daisy chain resistance was measured on test samples at the following temperatures and dwell times in air: 125ÁC: at hr. 0, 8, 16, 24, 32, 40, 48, 72, 96 and -70 ÁC: at hr. 0, 8, 16, 24, 32, 40, 48.

Polymer Bumps

Figure 3. Chip-Coupler™: Chip- and wafer-scale interconnections with Modecularly Flexible Dielectric

Resistance of thermoplastic polymer bumps increased at 125ÁC and decreased slightly at -70ÁC, with increasing time. The change was reversible. The resistance variations measured were in the range of 0.200-0.300 ohms (see Figure 1). The resistance variations were comparable to the variation of control lines without bumps. We concluded, therefore, that the resistance variation of the bump material was negligible during temperature storage at high and cold temperature. No failures (open or short circuits) were observed. Temperature Shock Test

Each daisy chain resistance was measured at RT on various test samples after the following temperature cycles: -65ÁC to +150ÁC, 100 cycles, 10 min dwell at each cycle, 10 second transitions.

Bump resistance variations during temperature shock tests for thermoplastic material were in the range of 0.04 ohms at 150ÁC and -0.02 ohms at -55ÁC at the end of the 100th cycle. The resistance variations were within the variation of control locations without bumps.

We believe therefore, that the resistance variation of the bump material was negligible during temperature shock. We did not observe the increased resistance leading to temporary open circuits during cold shock below -30ÁC that was observed on thermoset bumps. No failures (opens or shorts) were seen.

Temperature and Humidity Storage

Each daisy chain resistance was measured at RT on various test samples after the following temperature and humidity storage: 85ÁC, 85 % humidity, 168 hr. (JEDEC Spec 22 Method A 101).

We prepared two sets of samples for the 85/85 tests. One set was coated with 25 microns of Parylene. The 85/85 tests were conducted at RGA Labs. The average resistance variation was about 0.200 ohms. The resistance variations were comparable to the resistance variation of control locations without bump daisy chains (straight-through metal lines).

Non-coated samples performed as well as the Parylene-coated samples. Under more severe conditions, however, organic coatings (such as Parylene) might be required to minimize the interactions with the ambient and to contain potential silver migration.

No failures were observed for thermoplastic bumps. We did not notice failures as reported previously for thermoset polymer bumps.

Both the electrical characteristics and contact resistance of these §exible, ultra-conductive adhesive joints (U.S. patent #4,695,404) are similar to those of the solder joints. Conductive bumps with this solder-replacement adhesive may be deposited with various methods similar to those used with solder pastes. This solder-replacement material permits much finer bump features and pitch, i.e., bumps with 75 micron diameter and 150 micron pitch were deposited consistently on 150-mm and 200-mm wafers.

Interconnection

Figure 4. Low cost chip-and-wafer-scale packaging with the Chip-Coupler™ flip-chip interposer showing heat spreader

The physics of interconnection joints formed by conductive adhesive is Van Der Waal in nature. There is no chemical or atomic link between the adhesive and the contact surfaces. Polymer molecules are not hermeticly sealed against oxygen; thus the contact surfaces are susceptible to oxidation changes. Oxidation resistance of contact surfaces is a necessity for the proper functioning of these §exible conductive joints. Good contact surfaces are much the same as those used for solder bumps. Typically, nickel-gold, nickel-gold-palladium, or other suitable combinations with suitable thicknesses will be applicable.

Unlike the process of soldering joints, however, thicker gold will not have a negative effect on the integrity of the interconnection joints made with these ultra-conductive §exible adhesives.

Typical silver conductive fills are subject to migration. A low viscosity underfill with §exibility and molecular stability similar to silver is recommended for such protection. We have incorporated other custom fillers of gold and palladium into our specialty polymer adhesive for solder replacement §ip-chip interconnections (see Figure 2).

Interconnection and bonding with this solder-replacement adhesive were achieved instantly at temperatures below 220ÁC. This specialty polymer chemistry has a high thermo-gravimetric degradation of over 450ÁC and easily withstands passes of soldering and other high temperature operations involved in building electronic components.

Alternative Approach

Figure 5. Chip-Coupler fabricated with vias and lead routing

Our second approach, which employs a molecularly §exible dielectric with embedded metallic wiring, is attractive because it uses traditional intermetallic solder joints. In this Chip-Coupler method, conductor columns of pure copper (or other metals) are embedded in a molecularly §exible dielectric to form a solderable interposer, which couples the contact pads of the chip to those of the laminate.

These solderable interposers may be fan-out, or identical solderable conductor columns, to those of the chip-contact pads (see Figure 3). The molecular §exibility of the dielectric and that of the conductors maintains electrical interconnection with successful mechanical decoupling to provide the necessary reliability.

Thermal management of high-power devices can also be easily accommodated with the use of a heat spreader lid attached directly to the backside of the die (see Figure 4).

Traditional §exible interposers which employ thin polyimide film and a TAB-like interconnection (for example, Tessera's µBGA¬), use traditional via creation techniques such as laser, plasma and other mechanical drilling methods.

The molecularly §exible interposer is much easier to fabricate with both vias and lead routing with the use of dielectric that will polymerize into a designed matrix of conductor vias (see Figure 5). The cost per lead of this form-in-place method of interconnection between dielectric surfaces is estimated to be lower than $0.05 for larger volumes. Even for the relative lower quantities, the cost per lead is well within $0.10.

Chip-Coupler technology eliminates the need and problem of using underfills both at the component and board levels. Comparable interposers of the same interconnection density cost two to three times more than the solution provided with this intrinsically §exible substrate having low dielectric constant and dissipation. Besides using the Chip-Coupler interposer for the construction of fine-pitch components, good parts may be directly soldered onto the proper Chip-Coupler interposer for final component construction.

Chip-Coupler technology uses a §exible dielectric that has a dielectric constant of 3.8 and dissipation of less than 0.01. The modulus of elasticity is 20,000 psi with elongation of more than 100% and glass transition at -55ÁC. The adhesion to copper is more than 3000 psi with no change in bonding after 85ÁC/85%RH aging. The thermal stability is high and demonstrates a thermogravimetric degradation temperature of higher than 425ÁC to allow multiple soldering operations with non lead or lead solders. Conductor pitch of 10 mils or more can be produced easily with a thickness of dielectric 3 mils or thicker. The thickness of the dielectric may be as thick as 60% of the pitch.

Dr. Chung is the founder and CEO of AI Technology. He gradua-ted with degrees in physics and material sciences from Rutgers University, and worked at the David Sarnoff Research Center, Princeton from 1980-1985. Readers may contact him by e-mail at ait@aitechnology.com, phone 609.799.9388, fax 609.799-9308.