January - February 1999 - ChipScale Review

January - February 1999


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Substrate Requirements for Chip-Scale Packaging

By Dr. Rao Mahidhara, Technical Editor

Over the past 30 years, electronic packaging has embraced major changes brought about by changing market forces. First, mainframe computers drove interconnection technology in the 60's and 70's. Then, in the 80's, personal computers again changed interconnect requirements. Today, handheld and portable products lead the way. The most important factors related to portable consumer products, which bring a new level of complexity, are component density, physical size, weight and performance. This complexity arises, in part, from the growing high-speed performance demands of new CMOS technologies, which exhibit steadily decreasing feature sizes.

Feature sizes have declined, over a very brief period, from 10 µm to 0.6 µm and on to 0.25 µm, which is still not the bottom limit. ICs with 0.25 µm are finding widespread use for different classes of memory, such as DRAM, SRAM and flash. They are also being employed for logic devices and the new generation of miniaturized CMOS circuits.

A program for portable products at the Microelectronics and Computer Consortium, Austin, Texas, has benchmarked various leading-edge products and advanced board technologies

The most important factors related to portable consumer products, which bring a new level of complexity, are component density, physical size, weight and performance. This complexity arises, in part, from the growing high-speed performance demands of new CMOS technologies which exhibit steadily decreasing feature sizes.

Board Wiring Density Increasing

According to the MCC program, in the year 2000 there will be commodity PWBs with up to 1,153 leads/inch2 connected by 300 inches/inch2 of wiring. Leading-edge products, on the other hand, will boast up to 1,859 leads/inch2 connected by 546 inches/inch2 wiring by 1998. By the year 2000, boards will contain an estimated 17,760 leads/inch2 connected by 2840 inches/inch2 of wiring.1 This wiring density increase represents a 2x hike for 1998 and a 9x increase for advanced boards by the year 2000.

Market Trends

Figure 1. This technology roadmap for various products shows advanced PWB requirements. (Source: TechLead Corp.)
Figure 2 shows the trends followed by different markets. It's clear from this illustration that new electrical products, such as desktop PCs, notebooks, modules, camcorders and cellular phones will become more complex, even while shrinking, and their components will be forced to do likewise. New products incorporating advanced packaging technologies will demand advanced interconnect technologies. The products shown in Table 1 will contain a variety of assembly densities ranging from an average of 30 connections/inch2 to an average of 600 connections/inch2.

In the next few years, we will see a resurgence of new, space-saving semiconductor packaging technologies in a variety of form factors, including BGAs, CSPs, flip- chips and fine-pitch parts—all demanding increased interconnect density.

One of the traditional roles of packaging has been to form the transition from the high-density interconnections at the chip's perimeter to the lower densities available on the board.


Figure 2. Assembly densities for six different electrical products (Source: TechLead Corp.)
The new packages can present new challenges to the interconnect world. In chip-scale, area-array methods, a small form factor is needed, and there is no mechanism to accommodate the transition from the chip's I/O density to the board's density. This shifts the burden of "fanning out" the interconnections entirely to the PWB interposer. Design rules and wiring densities in PWBs can also become quite demanding and may exceed what is normally thought of as through-hole PWBs, leading to high-density interconnect structures (HDIS).

Moreover, since lithographic features on PWBs are coarser than those on the ICs, boards typically are multilayer boards (MLBs) and use multiple layers rather than finer features to obtain increased interconnection density.

Multiple Board Layers Needed

Clearly, as chip sizes decline below 3-mil outer lead pitch (actual or effective), routing interconnections to any chip-scale package will require multiple board layers just to place enough wires under the chip.

Gaining electrical access to the underlying levels of wire requires vertical connectivity, which is provided by the vias. Since via and pad can block routing channels, each year these parts become smaller. The reduction of via and via-pad sizes effectively increases the PWB wireability.

The reduction of vias and via-pads, coupled with the line-width and line- space reduction, gives PWB designers the capability of decreasing size, weight and layer count in new products.

As circuit features shrink, however, commodity PWBs and conventional testing technologies will both be inadequate. All components mounted on a PWB place a wiring demand on the board that must be accommodated by the board's wiring capacity to complete all connections. Greater wiring capacity, however, increases overall cost for the board and, therefore, the package.

Via Density

The evolution of PWB technologies shows that via density is the major driver. However, time-to-market, improved electrical performance, introduction of new types of area-array packages, increased two-sided SMT densification and RFI/EMI reduction should not be discounted.

Product Type Desktop PC Back & Box Notebook PC Modules PCMCIA Camcorders Analog/Digital Cellular Phones
PWB Type 2S2P PWB Advanced Substrates >95% SMT Components Thin FR4 Advanced Hybrid Components Advanced Substrates w/Blind Vias
Design Objective Fixed Form Factor/ Function at Lowest Cost Thermal Mgmt.
High Speed Signals
Low Power Consumption
Mixed Analog and Digital
Maximize Functions Within the Fixed Format Minimize Component Size Minimize Size and Weight
Applications 0.55mm Pitch ASICs QFP, BGA, & Modules QFP, BGA, CBGA & CSP 0.4mm Pitch TQFP, TCP, BGA & Modules TQFP, TAB, CSP & Flip Chip TQFP, BGA & CSP TQFP, TAB, CSP & Flip Chip
Assembly Single Sided Double Sided Double Sided Double Sided Double Sided in flex Double Sided w/ RF Needs
Connections/Sq Inch 30-80 40-180 40-240 100-260 100-600 100-400

Table 1. Design Characteristics by Product Type

The first generation of boards was the single-sided, etched copper board. The next generation was double-sided. Methods employing mechanical drilling (or punching to form vias) and metalizing them through the entire stack advanced board technology into the third generation. The large size and the low density of these methods lead to a mismatch between horizontal and vertical connectivity that limits routing capabilities. Today's fourth-generation HDI board technology is characterized by blind and buried microvias and sequentially manufactured layers. These layers either stand alone or rest atop conventional third-generation boards.

Characteristic Current Capability Future Capability
Materials (low loss, low Dk, high Tg) GETEK (0.0019, 3.6, 190°C);
Cynate ester (0.0016, 3.4, 260°C);
Polyimide Aramid (0.0013, 3.6, 320°C);
Liquid Crystal Polymer (0.001, 2.8, 280°C)
RCC (0.0019, 3.8, 180°C)
Liq thermoset resins, low Dk,
PPO (0.001, 3.1, 220°C)
Extruded thermoplastic resins
Photodielectrics, Ciba Probelec 81/7081
Minimum Material Core Thickness 0.050 mm (0.002") 0.025 mm (0.001")
Typical Board Finished Thickness 0.6 mm (0.024") 0.3 mm (0.012")
Choice of Surface Finish Hot air solder Leveling;
Organic solder preservative;
Selective solder coat;
Electroplated gold
Electroless tin
Electroless palladium;
Fine-Pitch selective solder bumps;
Electroless nickel/gold
Minimum Component Pitch SMT: 0.15mm
BGA: 0.35 mm
DCA: 0.5 mm
SMT: 0.1 mm
BGA: 0.45 mm
DCA: 0.25 mm
Solder Mask Tolerance 0.050 mm (0.002") 0.037 mm (0.0015")

Table 2. Printed Wired Board Capabilities.

The densification of substrate attachment pads, measured as the number of solder interconnections per square inch, is another indicator of HDI substrates. The Semiconductor Industry Association roadmap suggests that the number of solder interconnections is increasing from more than 200 pads/inch2 in 1995 to over 1,200 pads/inch2 beyond the year 2005. For example, the Sony Handycam (introduced in October 1996 and currently in high-volume production) exhibits over 500 interconnections/ inch2 and corroborates the SIA roadmap data.

While low-I/O-density ICs (such as memory chips) can be readily accommodated using mature board technology (0.15 mm L/S), high-I/O-density, large microprocessors (I/O > 150) require state-of-the art PWBs with microvias or HDI printed circuits to provide sufficient wiring for chip-scale or flip-chip packaging.

Other important features needed for the assembly of ICs onto boards include:

  • Material physical characteristics (thickness, flexural strength, dimensional stability and CTE)
  • Surface finish
  • Solder mask performance
  • Solder mask registration
The features that make up printed circuit density (inches/square inch) are circuit traces, circuit spaces and via pads (or via holes and annular ring). Current PWB capability is shown in Table 2.

Preferred Laminate

BT (bismaleimide triazine), a resin-based laminate, has become the preferred laminate material for many manufacturers, although it is more expensive than the traditional epoxy-based laminates, such as FR-4, because of its high Tg (230ÁC-330ÁC), low dielectric constant (3.8 - 4.3 at 1 MHz) and good insulation characteristics (5 x 1014).

Feature (inch) Conventional Advanced Leading Edge State of the Art
Contact Pad Diameter0.0120.0120.0060.0055
Line Width0.0060.0040.0030.002
Spacing Width0.0070.0040.0030.002
Drill Via Diameter0.0180.0140.0090.006
Drill Capture Pad0.0280.0220.0160.014
Microvia Diameter--0.0040.002
Microvia Capture Pad--0.0110.008
Layer Density (in./sq in.)50


0.050" channel2060120200
0.025" channel--80150
Availability (world wide)MOSTMANY˜6526

Table 3. Typical Design Rules for Printed Circuits

Mitsubishi Gas and Chemical owns the lion's share of the world BT market, supplying about 100,000 m2/month.2 Meanwhile, General Electric, Hitachi Chemical and Matsushita have been promoting their alternate materials, which are, respectively, GETEK, MegTran and MCL-679. These alternates are epoxy-based, high-temperature materials which Hitachi also calls FR-4.5. Currently, BT substrates for BGAs and CSPs (pitches 0.5 mm to 2.54 mm) are fabricated by conventional PWB technologies involving hole formation by conventional drilling. A higher drilling capacity will be a requirement for future advanced substrates for BGAs and CSPs. A panel made of BT resin is hard and is not conductive to drilling small holes. Considerable time will be required to drill substrates made from BT resin to meet the hole-density needs (500,000 small holes/m2) of future substrates for new BGAs and CSPs.

A panel-plate, tent-and-etch process has been employed for hole-plating with 12-15 µm copper.3

Final substrates are tested using automated optical inspection to detect electrical opens and shorts using a bed-of-nails electrical tester or noncontact electron-beam tester. Visual inspection, using a microscope or magnifying glass, is also employed to complement final testing.

Design Rules

Four categories are used by the PWB industry: conventional, advanced, leading-edge and state-of-the-art.4 The design rules for these categories are shown in Table 3. (See Table 2 for the capabilities of conventional PWBs and future requirements for 1999 and beyond.) Conventional boards cannot handle grid arrays with high I/O or pitches below 0.5 mm.

Newer substrate technologies are based on build-up multilayer boards with microvia holes (MVHs) featuring an aspect ratio of about 1:1. The last two categories in Table 3 are specific to HDI substrates and are the basis of MVH technologies.

When board thickness does not decrease in proportion to the hole diameter, higher-aspect-ratio holes result, which can lead to reduced reliability. Again, the solution is to employ blind vias in the context of HDI printed circuits. (All the various MVH technologies provide approximately the same design rules.)

Obviously, the use of PWBs with design rules appropriate to advanced packages is critical. For example, lower I/O (<400), larger pitch (1.27 mm), peripheral-row array (up to four) BGA packages can employ less elaborate design rules and four-layer MLBs.)

If more or finer-pitch I/Os are required, the complexity of the PWBs escalates and may require microvia-based, HDI boards. The use of CSPs or direct-attach flip-chips usually requires HDI printed circuits.

MVH may take the form of SBVH (surface-blind via holes) and IVH (inner via holes). In some cases, SBVH may reach the third or fourth layer from the top. Build-up technologies are always accompanied by microvia-hole technologies. Thus, they are really synonymous with MVH methods.

Fabrication Technologies

Microvia technologies may be grouped into three fabrication methods:

  • Create hole, then make conductive
  • Create conductive via, then add dielectric
  • Create conductive via and dielectric simultaneously
With conventional MLB fabrication, the cost of drilling ranges from 25% - 35% of the total process cost. With mechanical drilling, on the other hand, the cost for fine-pitch BGAs and CSPs constitutes almost 50% of the process expense when holes are about 0.2 mm.

The cost of drilling holes less than 0.2 mm and down to 0.15 mm (also called MVHs), is prohibitively higher with mechanical drilling and can add to the overall PWB cost.5

Among the newer drilling techniques, laser (CO2, UV/Nd:YAG and excimer) and photochemical techniques are being actively pursued by several companies, with the prime objective to reduce the overall substrate processing cost. Drilling speed using the CO2 laser is about 230 - 250 holes per second. In addition, new T-CO2 lasers can produce more than 30,000 SBVHs per minute, unlike the UV/Nd:YAG laser.

In comparison, however, and unlike the CO2 laser, the UV/Nd:YAG laser can penetrate through copper foil and glass, but the speed of the Nd:YAG is only about 1/10th of the CO2 laser. This ability to penetrate is the result of the UV wavelength.6

Because of its ability for speed, the CO2-based laser is used by makers of high-end MLBs for panel composition, with resin only above the inner layer pattern. Meanwhile, the Nd:YAG is the laser of choice for substrate makers employing flex tape, because this laser is useful in penetrating through a relatively thin structure covered by two copper layers, such as flexible material.

Hitachi, Lumonics, Panasonic and Sumitomo all offer CO2 drills. Lumonics of Canada now offers a combination Nd:YAG/CO2 laser. Excellon and Exotech are suppliers of UV/Nd:YAG laser drills.

MVH formation by gas-microwave plasma (GMP) has been promoted by Dyconex of Switzerland and its licensee, Hewlett-Packard.

GMP has been used very successfully in space and military applications in both the United States and Europe. It is not used in Japan, but Dyconex has 16 licensees worldwide, giving it substantially more HDI substrate installations than any laser technology vendor.

Dyconex sells a basic plasma drill for as little as $55,000, compared to a laser drill that costs from $500,000 up. Consider, too, that a photodielectric facility may require $300,000 in equipment and facility charges.

Excimer lasers are another option for drilling HDI boards. This technology has been used for many years because of its ability to be masked into many beams. It is possible to drill 250,000 SBVHs/ minute with holographic phase mask or a multielement projection mask. The excimer laser can process limited materials and does an excellent job on polyimide film and aramid laminates.x This technology was pioneered with laser drilled, co-fired ceramic technology. Litel, JPSA and Tamarack make UV:excimer drills, to which JPSA can add either T-CO2 or diamond CO2 laser heads.

Many of these new technologies have been actively pursued in Japan, as evidenced by the list of laser and photovia technologies, shown in Table 4.

ProcessCompanyMaterialLines/SpacesVia/LandVia Process Diameter
DV-MultiNECEpoxy Film80-50/
80-50 µm
100/250 µmPhoto
IBSSIbidenEpoxy Film75-50/
75-50 µm
150-100/
250-150 µm
Photo
ALIVHMatsushitaAramid Epoxy60/90150/300 µmLaser
PERL (Plasma Etched Rdistribution Layers) Hewlett-Packard HADCO Worldwiser Epoxy film PI/Aramid 75/50 µm and 75/50 µm 125-90/250-165 µm> Plasma Plasma/Laser
Build-up Substrate Fujitsu Epoxy 40/40 µm 90/140 µm Photo
VB-2 Victor Epoxy 10-95/100-75 µm 200-100/µm Photo
B2IT Toshiba BT Laminate 90/90 µm 200/300 µm Paste/Bump
Multi-Layer Build-Up Shinko Multiple 40/40 µm 50/110 µm Laser/Photo
SLC (Surface Laminar Circuit) IBM Yasu Epoxy Liquid 75/50 µm anD 125-90/250-165 µm Photo
Hitavia Hitachi
100/100 200/500
Viathin Sheldahl PI 50/37.5 µm 60-25/140-75 µm & 85/50/200-165 µm Laser
ViaPly CTS PI/Aramid 75/75 µm 125/125 µm Photo
TLPS Ormet PI 50/50 µm 25/200 µm Photo
DYCOstrate Dyconex PI 100/125 µm 75/300 µm Plasma

Table 4. Key High-Density Substrate Technologies

In all of these laser processes, the hole formation is one at a time (except with the excimers), no matter how fast the drilling speed is. Therefore, each additional hole increases board cost. This fact warrants alternative approaches to via formation, such as ñmass via generation processes (MVGP)," which offer low cost and efficiency in a production environment.

An elegant example of MVGP is IBM's Surface Laminar Circuit or SLC technology. SLC was developed and is being manufactured as a typical sequential build-up board with a liquid photo-imageable dielectric resin in layers.

When the number of holes required is very high, photovia processes, such as SLC, are more economical than laser drilling, because many vias can be produced in a batch photolithographic step. A number of board makers are now mass-producing MLBs with MVHs by a photovia process (summarized in Table 4).

In a market dominated by rigid substrates for BGA and CSP applications, a new breed of substrates, which employs polyimide film as the circuitizing material (also called flexible tape), is rapidly expanding into the substrate market for assembly of fine-pitch packages.

Lightweight, thin, reliable 3-D interconnection and a host of other positive attributes have been used to describe the enabling quality of flexible circuits.

Among flexible circuits' attributes is that the flex-tape manufacturing is quite similar to that of the rigid substrate fabrication, except that flex-tape is handled roll-to-roll. Hole formation is by punching or laser ablation.

Conclusion

The complex job of selecting design rules and structures for PWBs is being driven by newer, high-density components. In addition, materials technology is at the heart of "build-up" technology and will enable the the next generation of PWBs with higher density, suitable to chip-scale packages.

The materials used in almost all these new PWB technologies share the same characteristics of non-glass reinforcement. This makes via generation by plasma etching, photolithography or laser ablation.

Next-generation build-up technologies will provide many challenges for board fabricators and their suppliers. Design tools and tooling techniques will have to be modified—which again warrants additional capital investment.

And new processes will have to be evaluated and installed. No matter what the change is, competitive costs will be the deciding factor. However, it will take several years before any single substrate technology emerges as the undisputed leader.

Acknowledgment

The author thanks Happy Holden of TechLead Corp., Boulder, Colo., for helpful advice during the preparation of this manuscript.

References

  1. H. Holden, "Microvia Printed Circuit Boards: Next Generation of Substates and Packages," IEEE Micro, Vol. 18 Nr July/August 1998, p.10.
  2. H. Nakahara, "Fabrication Techniq›es for IC Packages and High-Density PWBs are Merging," Chip Scale Review, September 1997, pp. 26 - 35.
  3. Ibid.
  4. H. Holden, "Matching Printed Circuit Board Characteristics to Advanced Area-Array Components," Advancing Microelectronics, September 1998, p. 18.
  5. H. Nakahara, "Fabrication Techniques for IC Packages and High-Density PWBs are Merging," Chip Scale Review, September 1997, pp. 26 - 35.
  6. H. Holden, Pivate Communiation


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