Amkor Iwate Co. Joint Venture Opens in Japan
Amkor Iwate Co. facility
Chandler, Ariz.-Amkor Iwate Co. Ltd., the joint venture assembly and test business of Amkor Technology Inc. and Toshiba Corp.'s semiconductor company, has begun operations near Kitakami, Japan.
The facility is sited at Iwate Toshiba Electronics Co. Ltd. Initially, Amkor will own 60 percent of the joint venture company. By the end of the third year, Amkor will assume 100 percent ownership. Under a long-term agreement, Amkor will continue to provide packaging and test services to Toshiba. [amkor.com]
OSE Increases IPAC Holdings to 68 Percent
Santa Jose, Calif.-The Integrated Pack-aging Assembly Corp. (OTC:IPAC) has signed a stock purchase agreement for $6 million with Taiwan-based IC assembler OSE. The pact calls for OSE, which is IPAC's majority owner, to buy some three million shares of IPAC Series B preferred stock, convertible into about 42 million shares of common stock.
With the transaction, OSE increased its IPAC holdings to 68 percent on a fully diluted basis. [ipac.com]
PSi Tech Earns ISO Rank
Manila-PSi Technologies Holdings Inc. recently announced that it has received ISO 14001 certification from the Germany-based ISO TUV auditing firm for its main plant in Taguig City, near Manila.
The company has also installed a comprehensive manufacturing execution system based on PROMIS, a popular automation software employed to track work in progress, from PRI Automation, Canada. Psi Technology plans to opens its third Manila-area-based plant in mid-year. In a separate announcement, PSi Tech said it has added ROHM Co. Ltd., its first direct Japanese customer, for power semiconductor assembly. [psitechnologies.com]
APack Technologies, Taiwan, Introduces Family of Chip-Size Packages
Hsinchu, Taiwan-APack Technologies Inc. has introduced a family of patented chip-size packages in the True Chip-Size Package (TCSP)/ True-Die Size Package (TDSP) format. The packages are produced at the wafer level.
The TCSP/TDSP is produced at the wafer level without underfill.
APack says it's primarily targeting the market for analog, memory and mixed-signal devices employed in cellular and portable computing applications.
According to Victor Batinovich, APack president, the company's wafer-level process results in performance "equal to or better, but many times less expensive, than virtually any other chip-scale or chip-size package."
Batinovich says the TCSP/TDSP format offers both low cost and true chip size/ die size. "It is 30-40 percent smaller and 60 percent thinner than any other CSP now commercially available," he claims.
The package is SMT-compatible with all existing surface mount CSP and die placement systems and will support device clock speeds up to 3 GHz, Batinovich adds.
The APack process produces TCE-compliant packages, he says, without the need for underfill. Prototypes and shorter runs of the new package format will be produced at Apack's U.S. partner, AIS, located in Morgan Hill, Calif.
APack also announced that Masayuki Ohi has joined the company as vice president for R&D and customer service, reporting to Yoshi Shimada, senior vice president of operations.
His duties include quality control and reliability functions, as well as customer service and R&D design and engineering for new products.
Ohi was most recently engineering manager for the Plastic Laminated Pack-age Division of Shinko Electric Industries, Nagano, Japan.
While at Shinko, he was in charge of inte-grating Intel's Pentium III into Shinko's flip-chip BGA line. [apack.co.tw]
ASE Licenses Flip-Chip, WLP Processes
Willow Grove, Pa.-Advanced Semiconduc-tor Engineering has signed an additional site license for wafer bumping technology and added a separate license for the Ultra CSP wafer-level packaging technology.
ASE initially signed a license for Flip Chip Technology's Flex-on-Cap wafer bumping and redistribution (RDL) technologies in May 1999.
The flex and RDL processes will be employed at ASE's recently expanded Penang, Malaysia, facility.
The Ultra CSP will be manufactured at ASE's Kaohsiung, Taiwan, plant and provides for documentation, training and engineering support from the K&S subsidiary. [aseus.com][kns.com]
STATS Introduces Stacked BGA for Wireless
Singapore-ST Assembly Test Services has introduced a near chip-scale package for the wired and wireless communications market.
Known as the Stacked Die Ball Grid Array (SDBGA), various ICs are combined in one package, reducing manufacturing cost, test time and circuit board real estate.
According to STATS, both the mounting area and weight of an SDBGA can be reduced as much as 70% over conventional packages.
Total SDBGA package height is typically 1.4 mm. Popular SDBGA sizes are 8x8 mm to 14x14 mm with pin counts between 80 and 140.
STATS points out that by stacking different ICs on top of one another in an SDBGA package, the chip size is retained with enhanced capability. [statsus.com]
Kingpak Assembles Flash for Silicon Storage Technology
Santa Clara, Calif.-Kingpak Technology has been selected by Silicon Storage Technology to the latter's Multi-Purpose Flash family of ICs in chip-scale BGA packages.
The assembler claims that the tiny 6x8 mm package outline with 48 leads is the industry's smallest package for flash memory devices of 2, 4 and 8 Mb. The memory is aimed at space-constrained applications. [kingpak.com]
ChipPAC Acquires VIKO Test Labs
Santa Clara, Calif.-ChipPAC Inc., formerly Hyundai's Assembly and Test division, has acquired 20-year-old VIKO Test Labs, with facilities in Santa Clara and Austin, Texas.
VIKO is ChipPAC's second acquisition since completing its leveraged management buyout from Hyundai in July 1999. Last year, ChipPAC bought Intersil's plant in Kuala Lumpur, Malaysia. [chippac.com]