July - August 1999 - ChipScale Review

July - August 1999

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Solder Flip-Chip and CSP Assembly System

By Robert Peter
Alphasem AG,
Berg, Switzerland

A new flip-chip bonding platform, designed to handle both flexible and rigid substrate CSPs, is geared toward high-volume IC assembly.

Recent industry developments indicate that a major transition from sampling quantities to high-volume production is taking place in chip-scale packaging. At least 100 different CSP designs are now in development, according to the JEDEC standards committee. Some of the designs opt for conservative, existing technology (such as wire bonding), while others demand new materials and interconnection technology.

Currently, CSPs are usually placed into one of four categories: flex substrate interposers, rigid substrate interposers, leadframes and wafer-level packages. Many analysts believe that CSPs based on flexible and rigid substrates will dominate, at least over the near term, until wafer-level packages achieve a measure of maturity.

Recent developments, together with input from customers and package-design houses, further indicate that a major transition is taking place in CSP technology. Volumes are expected to ramp, and prices for CSPs have come under considerable pressure. The early infrastructure, while suitable for CSP development and prototype work, is not cost-effective for high volumes. The shift to volume production will require new equipment. With the introduction of the Alphasem Swissline 9002 CSP platform, we have addressed the flexible and rigid substrate marketplaces.

CSP Outlook

Until now, the assembly volume of CSPs has been fairly low. In 1998, according to informed estimates, about 400 million CSPs were assembled worldwide, representing only 0.7% of the total IC packages produced. According to industry analysts, this situation will change rapidly during the years ahead. Most experts believe that CSPs, driven mainly by space constraints and electrical performance requirements, can deliver appropriate solutions for several applications, most notably RDRAM, SRAM and flash memory (1, 2). On average, we expect about 3.5 billion units to be assembled during 2002.

The Tessera µBGA™ Package

This widely adopted package is based on a flexible interposer (tape) and single lead bonding for electrical interconnect. See Figure 1.

The process initially proposed by Tessera uses heat on the die and the tape during die attachment. The inherent disadvantage of using heat is the speed limitation of the process and the negative impact on optical alignment and machine accuracy.

Alphasem's goal in addressing CSPs was to push cost-effectiveness to its limits, since this will ultimately define the success of chip-scale packaging. We investigated several process variations, together with integrated device manufacturers, subcontractors and package design houses, to identify an optimized approach. Figure 2 compares the patent-pending, cost-effective process developed by Alphasem (right) to the initial Tessera process, which includes heat on the die and tape.

Figure 1. Tessera µBGA CSP

Alphasem took a different approach from Tessera's when developing the SL 9002 CSP flip-chip bonder. The Alphasem process is an integrated solution, which includes inline dispense, die attach and cure. This combination saves floor space and minimizes material handling to assure high assembly yield. The die attach steps for the µBGA package on the SL 9002 CSP are as follows:

  1. Feed frames with tape from magazine.
  2. Dispense die attach adhesive onto nubbins (inline), utilizing Alphasem's field-proven, volumetric dispense technology.
  3. Pick and invert die.
  4. Present die to optical alignment system.
  5. Align bond pad to leads with X,Y accuracy of ±12 µm (±0.5 mil) and theta accuracy of (typically) ±0.1 degree.
  6. Bond die onto nubbins with tight control of planarity between die and tape.
  7. Cure die attach adhesive inline.
  8. Feed frames into magazine.
TI MicroStar CSP

This package is also based on a flexible interposer, as shown in Figure 3, and employs wire bond technology to connect die and substrate. This package design shows a more conservative approach, utilizing the fine-pitch traces on the tape but avoiding the risk of lead bonding and the issues associated with that technology, such as tape inaccuracies and warping. Due to the tight specifications on the package size (die size + 2 mm) and overall height (1.2 mm for 0.5-mm pitch), all the process requirements are pushed to the limit.

The most important assembly requirements are as follows:

Accurate Dispensing

The accuracy of the position and epoxy volume is critical for subsequent processes. Any epoxy spread to the wire bond pads, which are very close to the die, can cause open or weak wire bonds.

Figure 2. Alphasem's µBGA Assembly Process

Accurate Die Attach

A large deviation of the placement position can result in poor bondline thickness and epoxy spread. A related requirement is sufficient resolution of the optical alignment system to recognize the small fiducial marks on the flex substrate.

Recognition of Defective Sites

This requirement, which is discussed below as part of the STPBGA discussion, is also common.

The MicroStar packages are assembled today on Swissline 9002 HP (High Precision) equipment. This system achieves die placement accuracy of ±40 µm. This application is definitely less demanding than the Tessera approach, because die flipping is not necessary, and the accuracy requirements are lower than those for lead-bonded µBGA packages.


The STATS Small Thin Plastic BGA (STPBGA), based on a rigid interposer, is shown in Figure 4. The design utilizes wire bond technology to connect the die and the BGA substrate. Currently, it is the most conservative approach to chip-scale or near-chip-scale packaging, utilizing well-known BGA materials and flexible wire bonding technology. The drivers for this choice are low risk, low cost and a rapid time to market. The designs currently achieve die size plus 1.5 mm, and a die size plus 1.0-mm package will be ready by early 1999.#

Figure 3. The Micro Star CSP

Figure 4. Small Thin Plastic Ball Grid Array (STPBGA) CSP

The STPBGA package has many technical challenges, including thin molding (under 1.0 mm), thin die

(0.2 mm), low wire bond loop height and short wire bonding span (0.3 mm).

The key process elements for these packages are very accurate die attach placement and very short wire bond span, which reduces the distance from die edge to package edge. These requirements are very similar to those for the TI CSP, but there is another one that deserves closer attention. The STPBGA package employs an array-type BGA substrate, where it is necessary to detect reject sites within the matrix, and the defective sites are commonly marked with ink dots.

Alphasem utilizes the new PDI (pre-dispense inspection) camera to inspect a whole matrix at once without slowing the machine. This new feature permits reliable inspection of even very small marks due to high resolution and programmable illumination. The information regarding good and bad bond sites is then passed to the dispense and bond stations. The customer can decide to skip dispense and bond, or to bond a bad die onto the defective bond site. This helps to accommodate molding or encapsulation requirements.

Alphasem's Approach

The major design goal during the development of the SL 9002 CSP was to find a solution that fulfills the technical requirements without losing productivity or increasing equipment cost. This led Alphasem to adapt existing field-proven, high-volume production equipment for CSP assembly instead of using modified, expensive surface-mount equipment. We believe this approach offers the following advantages:

  • Typical throughput of 1700 units/hour (UPH)
  • Lower initial cost
  • Smaller footprint
  • Process integration and high degree of automation (integrated dispenser, wafer loader, substrate handling and curing)
  • Availability of all options required for high-volume assembly (bar-code scanners, wafer map, SECS interface, etc.)
  • New features like pre-dispense inspection to support array type substrates

Figure 5. Alphasem's Proprietary Die Flipper

Alphasem therefore upgraded existing equipment to fulfill the required process specifications by using the approaches described below.

Flip-Chip Module

The die-flip module must allow the inversion of the die without loss of throughput. This is achieved by flipping the die on the fly, between pick and bond positions, a feature that is utilized for µBGA package assembly. Alphasem's patented die flipper (Figure 5) has been on the market for several years and offers a quick and simple flip-to-nonflip conversion.

Figure 6. Alphasem's Optical Alignment System

Chip-to-Substrate Alignment

The optical alignment of the bond pads on the chip to the substrate is probably the most complex job in CSP assembly. It should not slow down the assembly process, but it still must ensure maximum die-placement accuracy to enable proper lead bonding. Alphasem chose a nontraditional approach by using a single camera system with split-field optics (Figure 6). This system simultaneously measures the chip and the substrate position directly before die attach.

This technology offers three major advantages compared with the standard solution using two cameras:

  • Maximum accuracy as the offset is measured directly before bonding (no blind travel)
  • Easier calibration
  • Lower cost, as only one camera system is used.
The optical alignment system used for CSP assembly on the SL 9002 CSP module is fully automated and will support array-type substrates. All relevant parameters are stored in the recipe; therefore product changes are fast and simple.

Process Integration

One of the weakest points of today's CSP assembly equipment, besides low throughput and high cost, is the lack of process integration. This means that the core assembly process-from substrate and wafer handling, to dispensing, to die attach and adhesive curing-is distributed to different machines. This system decentralization results in several disadvantages, including:

  • Large floor space
  • High initial cost
  • Extensive material handling, eventually causing dislocations and reducing yield
  • Split process responsibility among different equipment suppliers
The Alphasem solution provides full process integration with minimum floor space for the substrate and wafer handling, inline dispensing, die attach and adhesive curing. This is probably Alphasem's most important contribution to improved cost of ownership.

Cost-of-Ownership Considerations

Alphasem has performed a detailed cost-of-ownership study, with consideration of all relevant cost and performance factors, such as initial machine price, throughput, floor space and operator requirements. According to our study, Alphasem's new SL 9002 CSP can significantly lower the assembly-specific cost from $729/UPH to $264/UPH. This reduces the packaging cost of the die attach process, which contributes more than 60% to the overall cost.

Figure 7. BGA flip-chip package

The requirements for CSP and flip-chip assembly are, in many respects, very similar. Alphasem employs the same basic platform for flip-chip assembly. The main application processed on the Swissline 9002 FC is flip-chip into package (FCIP), a package based on high-density BGA substrates.

Flip-Chip Packaging Outlook

The constant trend to integrate more functionality and to reduce feature sizes on the IC is pushing the overall performance envelope for ASICs and microprocessors. To deal with these performance increases, IC packaging must result in improved electrical performance and interconnection density. The logical choice for advances in speed, electrical performance and I/O is the shift to flip-chip technology.

The assembly of flip-chips onto singulated (or matrix BGA) substrates is a very common choice today. More than 70% of the FCIP units assembled this year will be onto rigid, high-density BGA substrates. In the future, it is likely that this percentage will drop slightly, due to the use of flip-chip technology for CSP packages. Nevertheless, the growth rate of BGA flip-chips will be considerable during the next three years.

The package shown in Figure 7 uses solder for interconnection to the substrate. This technology was developed and applied by IBM in the late 1960s and is known as the C4 (Controlled Collapse Chip Connection) process. This process employs a solder composition requiring high reflow temperatures.

The respective products based on ceramic substrates were rather expensive, high-end applications. Today, where costs are a key driver, other solutions are pursued. With the introduction of high-density BGA substrates, the use of a eutectic solder composition for interconnects has emerged. The lower reflow temperature for eutectic solder permits reliable reflow flip chips on high-density substrates without any negative effects (warping and other failures).

Although there is considerable effort spent on alternatives to solder (stud bump bonding, anisotropy, and conductive adhesives, etc.), we believe these processes will not become mainstream. Some of them might have short-term advantages for prototyping low volumes, but most compromise electrical performance and mechanical strength. Another disadvantage that is common to most of these alternatives is the lack of self-alignment.

Figure 8. Swissline 9002 FC Inline Reflow Oven

The major focus of Alphasem's SL 9002 FC is cost-efficient assembly of eutectic solder flip-chips onto BGA substrates (singulated, strip or matrix) without compromising quality. The flip-chip assembly process on the SL 9002 FC is as follows:

  1. Feed substrate (strips, matrix or singulated) from destacker or magazine.
  2. Dispense flux onto bond pads inline.
  3. Pick and invert die.
  4. Present die to optical alignment system.
  5. Align die bumps to pads with X,Y accuracy of ±15-30 µm and theta accuracy of ±0.1 degree.
  6. Reflow package inline.
  7. Feed substrates into magazines.
According to the SIA roadmap for 1999, the typical flip-chip bump pitch is 180 µm, and the respective pad size is 70 µm On average, the placement accuracy required today is ±25 µm (±1 mil). The SL 9002 FC uses the same modules (volumetric dispense technology, die flipping and optical alignment) as the SL 9002 CSP, thereby providing ±12.5-µm placement accuracy. This approach ensures that the chosen platform can fulfill future requirements according to the SIA roadmap.

The major difference between the SL 9002 FC and the SL 9002 CSP is flux dispensing and the reflow process after die placement. Based on its long experience with inline reflow ovens, Alphasem has developed what it considers to be an optimum solution for inline reflow (Figure 8) of solder flip chips. The concept follows the overall design criteria for the SL 9002 FC to minimize floor space and therefore lower cost of ownership.

Reflow Oven

These are the crucial aspects regarding efficient solder flip-chip package reflowing:

  • Reflow package shortly after flip-chip attach to minimize handling (risk of package dislocation).
  • Provide necessary process features (ppm level, peak temperature, etc.).
  • Provide flexibility to quickly change setup (substrate sizes, reflow profile, etc.).
  • Minimize floor space.
A very efficient use of the oven capacity and an intelligent arrangement of heating elements enable us to build a short reflow oven. This was mainly due to the fact that we built an oven for leadframes, not for PC boards. The oven is tailored for the substrate sizes we process on the SL 9002 FC and minimizes floor space, N2 consumption and cost.

The oven includes heating elements on the bottom, hot gas inlets and top heaters, which permit very efficient processing of even singulated packages in carriers. The temperature range goes up to 400ÁC, and adequate sealing ensures minimal oxygen levels in the reflow zone, contributing to the reliability of the final product.


With CSP and flip-chip volumes starting to increase, newly developed and optimized assembly equipment is now becoming available. These new machines for volume production can significantly reduce IC packaging cost and therefore help to make the respective products more competitive in a cost-driven marketplace. The savings are mainly due to lower initial cost, higher throughput and smaller floor space, which ultimately result in lower cost of ownership.


Electronic Trend Publications, Advanced IC Packaging Markets and Trends, San Jose, 1998.

TechSearch International, CSP Markets and Applications, Austin, Texas, 1998.

Mr. Peter is product manager for Alphasem AG, which recently became a subsidiary of Universal Instruments. He received his BSc in precision mechanical engineering in 1989 from the Neu Technikum University in Buchs, Switzerland. Prior to joining Alphasem, he worked for KLA-Tencor Inc., Milpitas, Calif. Readers may contact him at peter.r@alphasem.com, by phone at +41.71.637.63.63 or by fax at +41.71.637.63.64.

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