IWLPC Videos

IWLPC 2011 — Exploiting the 3rd Dimension

By Ron Molnar, [AZ TECH DIRECT]

Jointly hosted by SMTA and Chip Scale Review, the International Wafer Level Packaging Conference (IWLPC) held October 3 — 6, 2011 in Santa Clara, CA validated the growing demand for more IC functionality in smaller IC packages by exploiting the 3rd dimension.

Figure 1: SMTA reported a 20% increase in attendance at IWLPC 2011.

"The SMTA was very pleased to see a 20% increase in attendance at IWLPC." Noted SMTA Administrator, JoAnn Stromberg, "In conjunction with Chip Scale Review we were able to organize another strong technical program focused on leading-edge topics such as 3D, wafer level, and MEMS. With a sold out exhibit floor, outstanding speakers, and enthusiastic attendees we look forward to 2012 and another strong IWLPC."

This year's event, organized by Conference Chair, Andy Strandjord of PacTech USA, and Technical Chair, Luu Nguyen of Texas Instruments, consisted of 29 technical presentations organized in three parallel tracks, two panel discussions, six half-day tutorials, a poster session, two morning plenary sessions, and it was highlighted by an entertaining dinner keynote speech from Raj Master of Microsoft.

Exhibit Hall "Sold Out"

Figure 2: John Crane of Boschman has a captive audience from Agilent.

Generous Sponsors

Helping to make IWLPC the best industry conference on wafer level packaging were seven generous corporate sponsors. They were led by the Platinum-level sponsors, Amkor Technology, EV Group, and NEXX Systems. Gold level sponsors included Nanium, PacTech, STATS ChipPAC, and SUSS MicroTec.

Figure 3: At the STATS ChipPAC exhibit, Steve Wofford, Sr. director of worldwide marketing communications explains the company's latest WLP offering to an interested attendee.

Amkor Technology, Inc. is one of the world's largest providers of advanced semiconductor assembly and test services. They offer a suite of services, including electroplated wafer bumping, probe, assembly and final test. Amkor is a leader in advanced copper pillar bump and packaging technologies which enables next generation flip chip interconnect.

Figure 4: Curtis Zwenger, Amkor, discusses the company's latest TSV and copper pillar flip chip technologies.

EV Group, Inc. provides leading-edge wafer processing equipment for MEMS and Microfluidics, advanced packaging, compound semiconductor/MOEMS, SOI, power devices and nano-technology applications. EVGs product portfolio features double sided mask/bond aligners, wafer bonders for anodic silicon fusion, thermocompression and low temp plasma bonding, wafer/mask cleaning systems, photoresist spin/spray coaters and developers, hot embossing and nano-imprinting systems, and defect and particle inspection systems.

Figure 5: Garret Oakes, director of technology, EV Group, talks about the company's recent expansion at its world headquarters in Schaerding, Austria.

NEXX Systems has pioneered economical and flexible solutions addressed specifically to wafer level packaging (WLP). NEXX has become a global leader in the design and manufacture of advanced packaging processing systems that enable smaller and faster consumer electronics.

Figure 6: At Nexx Systems - John Bowers VP worldwide sales meets with Michael Schneider of ECI.

Attendance Grows Nearly 25%

Interest and activity in the area of wafer level packaging (WLP) continues to grow. This year's conference drew 460 attendees — up nearly 25% over the 370 registrants for the 2010 event. Participation from the international community also continues to grow. IWLPC 2011 drew attendees from 15 countries — led by the United States, Germany, Japan, Korea, China and the United Kingdom.

Popular Tutorials

The organizers were proud to offer six half-day tutorials to 92 students by a number of well-known and respected industry leaders as a means of educating those unfamiliar with wafer level and advanced packaging technologies.

The two most popular tutorials were "Wafer Level Packaging" by Luu Nguyen, Ph.D. of National Semiconductor and "TSV and Key Enabling Technologies for 3D IC/Si Integration and WLP" by John Lau, Ph.D. of Industrial Technology Research Institute (ITRI).

Talking Technical

Figure 7: Keith Cooper, SET North America, delivers an interesting talk on updated processes collective hybrid bonding for C2W processes.

Three parallel tracks of technical presentations were offered again this year covering WLP, 3D and MEMS topics. In total, there were 29 presentations. Judging by attendance figures, the most popular session was definitely Session 1 — Advanced Wafer Level Packaging Technologies, followed closely by Session 2 — 3D Process Advancements Part I, Session 4 — Fan-Out Wafer Level Packaging Technologies and Session 8 — 3D Process Advancements Part II.

Stimulating Plenary Sessions

Figure 8: Peter Ramm, Fraunhofer EMFT, introduces plenary speaker, Matt Nowak Qualcomm.

Prior to each day's technical sessions, attendees were treated to a stimulating morning plenary speech. The first was "High Density TSV Chip Stacking: Fabless Infrastructure Status" by Matt Nowak of Qualcomm. He presented some examples of several chip stacking partitions that are reportedly in development for productization, and discussed the progress made with respect to previously perceived challenges. Mr. Nowak went on to say, "Especially critical for the productization of high density TSV technology for high volume mobile wireless applications will be the readiness of the fabless supply chain infrastructure, including industry standards, supply chain business models for stacked memory cubes, and competitive pricing."

Figure 9: Vern Solberg of Invensas, is among a full house tuned in to John Lau's plenary talk.

The second plenary talk was "Evolution, Challenge and Outlook of 3D Si/IC Integrations" by John Lau, Ph.D., of ITRI. He explained the difference between 3D IC packaging and 3D IC or Si integration was that integration incorporates through silicon vias (TSVs). Dr. Lau covered the origin and evolution of 3D integration, technology development roadmaps, and he proposed a few generic, low-cost, and thermally-enhanced 3D IC integration System-in-Packages (SiPs) with various passive TSV interposers for small form factor, high performance, low power and wide bandwidth applications.

Lively Panel Discussions

Figure 10: An unidentified attendee queries the infrastructure panel, which was moderated by Simon McElrea, Invensas.

This year's IWLPC program included two panel discussions that provoked quite a few questions and debate among the panelists. "3D Infrastructure Issues for Technology Adoption", moderated by Simon McElrea of Invensas Corp. brought together a distinguished panel consisting of Sesh Ramaswami, Ron Leckie, Peter Ramm, Ph.D., Andre Rouzaud, Ph.D., Jan Vardaman, and Jim Walker.

"Will 2.5D and 3D Compete or Coexist?" was the title of the second discussion with panelists Scott Jewler, Ron Huemoeller, Phil Marcoux and Rao Tummala, Ph.D., moderated by Francoise von Trapp of 3D InCites. Each panelist made a short presentation and stated their case before the floor was opened for questions. The consensus opinion favored coexistence of 2.5D and 3D integration.

Figure 11: The 3D Panel discussed 2.5D vs. 3D technologies. (L-R) Phil Marcoux, consultant, PPM ; Ron Huemoeller, Amkor ; Scott Jewler, Powertech Technologies ; Rao Tummala, Georgia Tech's 3D PRC ; and moderator, Francoise von Trapp, of 3D InCites and Chip Scale Review.

Entertaining Keynote

Figure 12: Raj Master, General Manager for IC Packaging, Silicon Operations, Quality and Reliability for all hardware products at Microsoft entertains the dinner crowd with his keynote speech titled "Thermal and Power Considerations in Consumer Electronics."

Following Wednesday night's dinner, Raj Master, General Manager for IC Packaging, Silicon Operations, Quality and Reliability for all hardware products at Microsoft gave an entertaining keynote speech titled "Thermal and Power Considerations in Consumer Electronics." He kept the audience laughing with timely jokes, amusing examples, and funny illustrations while describing the very serious thermal management challenges facing 3D IC packaging and integration as computing products strive to operate faster and shrink in size. Thermal management can no longer be addressed solely at the system level using heat sinks and fans inside the product enclosure. Heat must be dissipated at the device level and must be capable of withstanding shock, drop impact, and bending often encountered by portable products.

For the first time this year, IWLPC provided video coverage of some of the plenary talks, keynotes, and platinum sponsors. Clips can be viewed at www.iwlpc.com

Save the Date IWLPC 2012

IWLPC 2012 will have an expanded exhibition hall when it moves to the Doubletree Hotel in San Jose, CA on November 5 — 8, 2012. Many of today's WLP challenges will be addressed in the coming year. Don't miss next year's event to learn about all the progress.