Technology and Strategic Business Leader to Guide Leti in Digital Era
GRENOBLE, France – Nov. 28, 2017 – Leti, a technology research institute of CEA Tech, today announced that Emmanuel Sabonnadiere has been named CEO, succeeding Marie-Noelle Semeria.
Sabonnadiere, who has more than 25 years of executive leadership experience in a variety of large technology environments, joins Leti from CEA Tech, where he led the industrial-partnership program. He brings a strong background in new-technology development with broad private-sector expertise in operational excellence, team building and guiding multicultural organizations in business transformation in Europe and globally.
As Leti’s chief executive officer, Sabonnadiere leads the activities of one of Europe’s largest micro- and nanotechnologies research institutes, which employs approximately 1,900 scientists and engineers, has a portfolio of 2,700 patents and has launched more than 60 startups.
“Success in today’s demanding international digital landscape requires a combination of deep technological expertise, advanced platforms, a commitment to customer and partner success and a shared excitement and agility about the new opportunities,” Sabonnadiere said. “This is where Leti is today, and I am very excited to join this world-class team to develop the solutions that will bring digital innovations to the benefit of leading technology companies around the world.”
Prior to joining CEA, Sabonnadiere was CEO of the Philips Lighting’s Business Group Professional in Amsterdam. From 2008 to 2014, he was CEO and chairman of General Cable Europe in Barcelona, and from 2005 to 2008 he served as CEO of NKM Noell in Wurzburg, Germany. Before that, he served as vice president of Alstom T&D for five years. Early in his career, he held multiple positions at Schneider Electric, including managing director of development for equipment units.
During his career, he has designed and implemented strategic plans for process optimization, product redesign-to-costs, market repositioning and system development.
Sabonnadiere holds a Ph.D. degree in physics from the Ecole Centrale de Lyon, an MBA degree from Ecole Supérieure des Affaires de Grenoble and an engineering degree in information technology from the Université Technologie Compiègne.
Sabonnadiere is a fully qualified instructor at the ski school in Les Ménuires, and member of the advisory board of IAC.
For additional information: Sarah-Lyle Dampoux, firstname.lastname@example.org
Heterogeneous integration paving the way beyond silicon scaling limits
Reflections on IWLPC 2017
By Louis Burgyan, LTEC Corporation
As in prior years, the in-depth presentations at this year's IWLPC, covering a broad array of the industry's critical challenges, did not disappoint. A series of keynote presentations and papers included a couple of major announcements that will be discussed below. Of special note, several keynote speakers focused on heterogeneous integration and the added complexities of migration to large rectangular panels. The session presentations reported impressive progress in material science, manufacturing processes, new equipment, metrology, and testing. A few selected highlights, only limited by the allotted space, are included below.
As semiconductor scaling is inching towards 7nm, fab investment costs increase exponentially. Meanwhile, key growth industries such as mobile, automotive, and Internet of Things (IoT) continually create new demand for the integration of diverse functions such as processors, memories, sensors, networking/communication, RF, power management, and discrete components that span the frequency range from DC to millimeter wavelengths. Monolithic integration of these functions is not practical, so package-level integration comes to the fore and the numbers reflect this. Next year, the semiconductor industry is expected to grow 4%, while the fan-out wafer-level packaging (FOWLP) market is expected to grow 36%. How will the packaging industry and its supply chain keep up? There is no simple answer to this multi-faceted question, however, the various keynote speakers and panelists provided attendees with excellent insights.
Naturally, the question of "round vs. rectangle" was in the minds of many presenters, panel members, and attendees alike. Will FOWLP technology remain on round wafers or migrate over to large rectangular panels? Will the success of one approach lead to the eventual demise of the other? The consensus is that both FOWLP and large FOPLP (600x600mm2 or similar) will coexist for the foreseeable future. There are good reasons for this: migration from WLP to PLP must be an evolutionary step. You start on WLP and move on to PLP after successful production experience is gained on the WLP line, with high yield and proven reliability. Several speakers alluded to the point citing similarity of the technical requirements and challenges along both paths. Some noted it would be a huge risk to commit to build a billion-dollar PLP fab line without prior WLP experience. The technical challenges, the large diversity of the integration tasks, potential fluctuations in customer demand, all represent enhanced risks, highlighting the need for careful assessment of market persistence and product selection. Currently, various sensor products, HDMI modules, optical communication modules, etc., appear to be viable candidates for fan-out packaging (FOP) or FOPLP, perhaps later followed by 5G antenna modules, RF system-in-package (SiP), even LED modules. The latter is a potentially very large market. Hopefully, in the coming years, we will see customer demand emerging from a broadening range of industries; however, for now, handset demand remains in the driver's seat.
FOPLP at the verge of volume production
Over the years, the industry became accustomed to Apple being tight-lipped about giving forward-looking guidance concerning its packaging needs. Only benchmarking and deep analysis can tell us what kind of packaging technology it actually did deploy. All the more reason to thank Richard (Kwang Wook) Bae, VP, Corporate Strategy & Planning Team at Samsung, who outlined the company's vision for moving forward with heterogeneous integration in his keynote. Samsung is developing its own in-house packaging technology—working on homogeneous and heterogeneous fan-out SiP solutions using redistribution layers (RDL).
The company anticipates a gradual disappearance of current package-on-package (PoP) solutions from the mobile space. Depending upon specific applications, both die-first and die-last approaches are envisioned. As other speakers, Bae stressed the many potential benefits offered by large panel FOPLP. For example, normalized to the throughput of a 300mm wafer line, up to 5.1x improvement can be achieved on large panels (no exact size was given), leading to significant cost savings. In addition, improvements in electrical, thermal performance, and form factor are also expected. Two processes, ePLP (chip first) and PLP-m (chip last) were mentioned by Bae, the latter intended for side-by-side multi-die SiP (Figure 1). Samsung is developing chip-first and chip-last FOPLP depending on the die size, number of dies and package structures (PoP, side-by-side, etc.). It has already developed key FOPLP technologies and plans for mass production early next year starting with chip first (Figure 1).
The ePLP version, intended for small dies, demonstrated good reliability results with RDL having 5µm L/S. My interpretation of the hints is that the initial product launch is likely to have 10µm L/S, perhaps less. Production starts next year on 510x500mm2 panels. Other process varieties and possibly larger panel sizes will follow later.
Construction of a 600x600mm² panel assembly line, also aiming for volume production next year, was disclosed by nepes Corporation. According to Jay Kim, presenting for Lewis (In-Soo) Kang, the company was able to leverage its considerable experience in 650x750mm² LCD panel fabrication, now in its fourth generation. He is confident that all major issues have been resolved. For example, warping is held below 1mm, and die shift is <10µm in the X direction and <5µm in the Y direction. The company prefers a large panel size and might consider upgrading to 650x650mm².
Tanja Braun of Fraunhofer IZM, presented the results of fabricating advanced LED devices on 457x305mm² panel for now, while aiming to upscale to 610x456mm² panel size later. This R&D feasibility project was initiated by the government of Germany for obvious reasons: 1) the LED lighting market is huge—LEDs enable energy savings and promote a green economy; and 2) large panel embedding, if successfully developed, could open the door for cost reduction thereby spurring wider adoption of LED lighting. Like other presenters, Braun's team also followed the "predictable" path by first implementing the project on 200mm wafers and then transferring it over to large panels. An "on-panel" die-shift measurement algorithm was used for die placement error correction including Θ correction. Double-sided Cu plating, 355nm picosecond laser via drilling, liquid molding, and other innovative techniques were used and evaluated in this project.
In his keynote presentation, B. J. Han, Chairman of STATS ChipPAC, offered a realistic assessment of the current state of wafer- and panel-level packaging technology, including his vision of the future. He noted that multi-layer RDL with 40-50µm bump pitch eliminates the need for the interposer, and can incorporate thin-film and other passive components; it is expected to remain the dominant approach for creation of 2D and 3D SiP solutions. Han suggested the vast majority of applications do not require 2µm L/S—what's needed on large panels are 5µm L/S and 100% yield. Han highlighted the simplicity of the chip-first, die face-down approach of the company's eWLB process supported by a solid supply chain. He further noted that the technology is easily scalable to any wafer size from 5in to the current 12in to 450mm if needed, on the same line. Having shipped over 1.5 billion units, eWLB serves as a solid foundation to expand into eWLB FOSiP. Currently, the company is starting to ship in the millions of FOSiP devices and expects significant growth in the coming years.
Materials and hardware
Overall, given the presentations and discussions at the conference, I saw signs of intense activity and progress all along the manufacturing ecosystem from materials research to lithography, wafer handling, plating equipment, and metrology, just to mention a few, as noted below.
Daisaku Matsukawa of Hitachi Chemical DuPont Microsystems reported on the development and evaluation results of a new low-temperature curable (200-225°C) polyimide/poly-benzoxazole (PI/PBO) that reliably supports 5-6µm L/S vs. the conventional material having 15µm capability and a 375°C cure temperature, resulting in lower shrinkage and less warpage. The new material shows improved flatness and chemical resistance.
Hitoshi Araki of Toray Industries reported the development of the LT-58000 low-temperature curable positive-tone photosensitive dielectric material having high elongation (40%) and low cure temperature (225°C) for wafer and large panel-level applications as an RDL dielectric. Both properties are essential for warp reduction. The material was thoroughly tested and proven reliable. It demonstrates 300mJ/cm² (i-line) sensitivity, good chemical resistance, good uniformity on 650x550mm² glass panels and supports 5µm L/S.
Hiroshi Matsui of SCREEN Semiconductor Solutions reported on the development of direct-write lithography equipment designed for patterning at 5µm L/S and beyond. This system measures the actual die location and applies corrections accordingly, including global Θ compensation.
James Welsh of Atotech discussed a new Cu electroplating method and associated tool for dual-side copper termination of power semiconductor devices for electro-mobility applications. A unique feature of the approach is its ability to enable simultaneous Cu plating on both sides of the power semiconductor device while maintaining independent and uniform thickness control on each side. Warpage-free dual-side Cu plating was produced using a thin Taiko wafer with continuous Cu plated on the back side. Up to 50µm continuous plating thickness was demonstrated. The dual-side method is significant in that it will lead to improved thermal electrical performance. The company estimates that the reduced process steps enable 26% wafer cost savings.
Christian Ohde reported on Atotech's newly developed electroplating tool, which was designed to meet the needs of large panel embedding up to 600x650mm² and presented results obtained on a 370x470mm² panel. The system uses multiple segmented anodes (not consumable) with reverse anode/cathode pulsed plating and adjustable current distribution. An iron redox system delivers the Cu from a separate reservoir. Cu plating results using 8/5µm L/S showed improved panel-scale uniformity at 1µm/min deposition rate.
Justin Oberst of Lam Research Corporation introduced the company's SABRE® 3D front-end/back-end electro-deposition system that enables the use of a thin seed layer of 600Å and a fine-line RDL with 2µm L/S and 4/2µm via aspect ratio. Used in conjunction with Ultratech equipment, a uniformity of <0.2µm was reported over the entire wafer.
Heard at the show
Aside from the many informative presentations, the Exhibitor Hall, networking breaks, and interactive presentations offered many opportunities to engage and learn.
As explained by Keith Best, Director of Application Engineering, Rudolph Technologies developed lithography equipment with an improved stage. The system is capable of handling large panels having warpage as high as 15mm, by multiple means: mechanical, and electro-optical. The application of mechanical force and vacuum reduces warpage during the lithography process to conveniently manageable levels. The residual warpage is handled by dynamic focus adjustment. Position errors of the die are handled by applying feed-forward metrology followed by dynamic error correction. The company also developed a method for detecting non-visual killer defects from transparent films such as photoresist (PR), polyimide (PI) and poly-benzoxazole (PBO) on wafers and panels. Its ultrasonic metrology equipment has capabilities suitable for back-end metrology. A picosecond laser is used to excite the area under test, and the reflected ultrasonic waves are captured for imaging.
All in all, the IWLPC 2017 reported an impressive array of progress throughout the manufacturing ecosystem, and many of the presenters reported significant advances in various aspects of packaging technology. The keynote presentations offered a reassuring perspective of the future of wafer- and panel-level packaging technology near term, as well as long term. For the first time ever, we could hear loud and clear from industry leaders the long-awaited confirmation that new components and subsystems manufactured on 600x600mm² panels will finally begin to roll out of the assembly lines next year. That will mark 2018 as a major milestone in heterogeneous integration. With these developments as a backdrop, next year's IWLPC (October 23-25, 2018; San Jose California) will surely be another exciting event, promising to offer valuable insights into the unfolding "more than Moore" era of heterogeneous integration. Mark your calendar!
Lajos (Louis) Burgyan received his Master's in Electrical Engineering from the Polytechnic U. of Budapest and is a retained consultant and technical advisor to LTEC Corporation; email email@example.com
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