There are certainly different understandings in the microelectronics community with respect to the definition of 3D heterogeneous integration. A very general definition is as follows: 3D integration of different devices such as a CMOS processor and a memory, for example. According to a more limiting specification, there would be, as well, the integration of different substrate materials as a necessary condition (e.g., GaAs/silicon). This article will provide a reasonable definition of heterogeneity in between: 3D integration of components with significantly different device technologies such as CMOS and MEMS.
There are various ways to vertically interconnect devices, where the most advanced technology is based on through-silicon vias (TSV) . Within wafer-level packaging, the platforms using TSVs are 3D IC integration and interposers ("2.5D"). Silicon interposer technologies are already mature and used in several production lines. Concerning "true" 3D ICs, the situation is different: the first companies are just beginning to take the step to production of 3D integrated products. This also provides a motivation to investigate the 3D IC patent situation. The large companies IBM, Samsung, Micron, TSMC, Hynix, and STATS ChipPAC are the leading players concerning the number of patents, as expected. On the other hand, relevant patents on 3D integration are also found among different academic institutions with ITRI being the top institute, followed by CEA (France) and Fraunhofer-Gesellschaft München (Germany). Apparently, Europe is strong in intellectual properties for 3D ICs too. Worldwide, memory-enhanced applications are seen as the main driver for 3D integration.
Fraunhofer has been working on 3D integration for almost 3 decades. Already in the mid-90s the Munich institute IFT (now EMFT) focused on 3D technologies for the use of known good dies by chip-to-wafer stacking (against at the time's mainstream concepts of wafer-to-wafer stacking). Understanding the necessity for combining research on both 3D technology and design at an early stage, we established a fruitful cooperation between the two Fraunhofer Institutes in Munich and IIS-EAS Dresden. 3D integration is now considered to be a new paradigm for the semiconductor industry.
Making 3D heterogeneous system integration possible
3D ICs are certainly the key enabler for 3D heterogeneous systems. Moreover, specific requirements are highly-reliable and robust processes for stacking, vertical interconnections for fully-processed devices by wafer-level 3D integration of known good dies (KGD), and being able to accomplish very small form factor and fine-pitch vertical interconnects. In particular, 3D-TSV technologies with freely selectable TSV positions have a strong demand for 3D system design methods to enable high performance of extremely miniaturized heterogeneous systems. The technology developments will have to deal with the following three basic conditions for heterogeneous integration: The components to be integrated will in general: 1) Be fully-processed devices (e.g., ICs with different complex back-end-of-line layers, sophisticated MEMS/NEMS or antennae devices); 2) Exhibit different chip areas; and 3) Not necessarily be fabricated with very high wafer yield.
As a consequence, robust and reliable 3D technologies based on chip-to-wafer stacking of KGDs are needed. To supply solutions for these requirements the European e-BRAINS consortium established the 3D Heterogeneous Integration Platform where technologies of the following relevant main categories (with definitions according to ref. #1) of 3D integration are provided to enable future applications of smart sensor systems : 1) 3D system-on-chip integration – 3D-SoC: TSV technology for stacking of thinned devices or large IC blocks (global level); 2) 3D wafer-level-packaging – 3D-WLP: embedding technology with through-polymer vias (TPV) for stacking of thinned ICs on wafer-level (no TSV); and 3) 3D System-in-package – 3D-SiP: 3D stacking of packaged devices or substrates.
Regarding TSV performance, the applications do not need ultra-high vertical interconnect densities as for 3D stacked integrated circuits – 3D-SIC (definition per ref. #1). Nevertheless, the lateral sizes of the TSVs are preferably minimized to allow for place and route for small "open" IC areas. Smaller TSVs are also preferred in order to reduce thermomechanical stress. e-BRAINS' focus is on how heterogeneous integration and sensor device technologies can be combined to bring new performance levels to targeted applications with high market potentials. The consortium, under coordination of Infineon and technical management by Fraunhofer EMFT, comprises major European system manufacturers (Infineon, Siemens, SensoNor, 3D Plus, Vermon and IQE), SMEs (DMCE, Magna Diagnostics, SORIN and eesy-ID), the large research institutions CEA Grenoble, Fraunhofer (EMFT Munich & IIS-EAS Dresden), imec, SINTEF, Tyndall and ITE Warsaw, and universities (EPFL Lausanne, TU Chemnitz and TU Graz). Target applications include automotive, ambient living and medical devices, with a specific focus on wireless sensor systems. Concerning the enabling 3D Heterogeneous Integration Platform, the e-BRAINS partners are working close together, where Infineon, Fraunhofer EMFT, imec and SINTEF are focusing mainly on 3D-SoC and 3D-WLP, while the French system manufacturer 3D Plus and Tyndall are focusing on 3D-WLP and 3D-SiP technologies.
In future sensor systems components, especially those used for the internet-of-things (IoT) applications, application-specific ICs (ASICs) and sensors will be integrated using dedicated 3D heterogeneous integration schemes. A 3D architecture of a wireless sensor system, for example, typically contains at least two IC devices: a sensor read-out and a communication ASIC (Figure 2a). In Figure 2b, an IoT-relevant application example is shown that implements additional security features to essentially hinder manipulation and misuse of secret/private data and counterfeiting of components (Fraunhofer EMFT trademark e-S³ense and patent pending); the robust face-to-face metallization is realized by intermetallic compound (IMC) bonding of the two ASICs. The sensor is connected by tungsten-filled TSVs through the ASIC 1. IMC bonding by solid-liquid-interdiffusion (SLID)  is used to mechanically and electrically interconnect the MEMS and IC devices in a robust and reliable way, as well as ensure sealing of the complete MEMS/IC stack.
Furthermore, a hierarchical modeling approach is necessary for multi-physics-simulations in different design phases and incorporating different sub-components. "The term "hierarchical model" refers in this approach to a set of multi-level models applied for the detailed description of system behavior implemented on various levels of abstraction. Basically, it consists of a principal model structure that is "loaded" with models suitable for a specific analysis. That means, for example, for early design phases a raw estimation of interconnect delays is completely sufficient; while later on, parasitic extraction and a detailed characterization of the timing of critical interconnect paths are crucial. The models for this spectrum of analysis have to be consistent on all levels of abstraction. Of course, these models are also correlated with the manufacturing technology and must be validated by measurements.
Range of applications
In general, all fields of ambient assisted living, smart buildings (e.g., wireless gas sensors for air quality systems), safety and security (e.g., IR imagers), biosensors and smart medical systems (e.g., active medical implants) are all foreseen applications.
More than 1 million pacemakers and more than 0.2 million defibrillators are implanted around the world each year. These numbers are increasing every year due to the increasing aging population and to the increase in implantation rates in emergent countries. Infusion pumps for diabetes or back pain represent more than 0.2 million devices implanted per year. Neurostimulators implanted for pain management, epilepsy, Parkinson's disease, obesity, or depression, are growing rapidly and currently more than 0.2 million devices are implanted each year. In 2010, 219,000 people worldwide had cochlear devices implanted. In the U.S alone some 900,000 people are believed to be deaf or near deaf. In India, there are an estimated 1 million profoundly deaf children, while only about 5,000 have cochlear implants. The main indication for pacemaker implantation is the atrioventricular block, which induces bradycardia or very slow, or no heart rate at all. In 2012, 4.89 million people were estimated to have this pathology worldwide. The global market revenue for pacemakers in 2012 was $4.3bn.Leadless pacemakers are expected to be revolutionary to the cardiac rhythm management industry by eliminating the need for lead replacement, which can generate an infection in 4% of the cases. In case of infection, the removal of the lead attached to the heart tissue is performed. This intervention might be critical and necessitates the patient hospitalization for several days in specialized care units. The state-of-the-art for the volume of a subcutaneous pacemaker is 8cm3. The state of the art for the leadless pacemaker volume is 1.5cm3. The first subcutaneous pacemaker was implanted in 1958. The first leadless pacemaker was implanted in a human in 2013. Leadless pacemakers need extremely miniaturized system integration to reduce the size. The use of 3D heterogeneous integration is one technique that satisfies this constraint. Leadless pacemaker (SORIN)
Figure 6a shows a leadless pacemaker. The diameter of the device is 6.5mm and the length is 27mm. All the electronics of the pacemaker are located in a 3D stacked heterogeneous module, built with 3D PLUS wireless-die-on-die (WDoD) technology, as represented in Figure 6b. The size of the 3D heterogeneous module is 2.3 x 5.2 x 7.3mm3. Figure 6c shows the different layers stacked to get the module represented in Figure 6b.
Two redistributed layers based on the embedded wafer-level ball grid array (eWLB) process were used. These layers have a thickness of 300µm and are populated with multiple back lapped chips having the same height. The other layers are PCB-based having surface mount devices (SMDs) of different heights. Manufacturing of 3D heterogeneous integrated modules for all the electronics of a leadless pacemaker has been proven effective. It can be concluded that 3D heterogeneous integration allows a reduction of the size of the electronics, which is necessary to fit inside the small volume allocated in a leadless pacemaker.
The next-generation pacemakers will deal with heterogeneous integration of energy harvesters and other passive components as super-capacitors. Corresponding low-temperature 3D integration processes have to be implemented in order to fulfill the challenging process temperature specifications for such components. For developing suitable technology solutions, i.e., for integration of durable energy harvesters to heterogeneous systems, SORIN, 3D PLUS, and Fraunhofer EMFT are continuing their cooperation in a new large European project called "MANpower" .
The main driver of 3D heterogeneous integration is certainly sensor integration. The system integration of sensors with ICs and passive components, such as energy harvesters, actuators and batteries, is becoming more and more important, especially for the high growth market area of distributed wireless sensor systems, which will constitute the key connected hardware infrastructure of the Internet of Things.
1. "Handbook of 3D Integration, Vol. 3," pp. 1-4, edited by P. Garrou, M. Koyanagi, P. Ramm, Wiley-VCH, 2014 (ISBN: 978-3-527-33466-7).
2. R. Beica, J.-C. Eloy, P. Ramm: "Key applications and market trends for 3D integration and interposer technologies," Handbook of 3D Integration, Vol. 3, Wiley-VCH, 2014 (ISBN: 978-3-527-33466-7).
3. "Best-reliable ambient intelligent nanosensor systems by heterogeneous integration – e-BRAINS," granted by the European Commission under grant agreement no. ICT-257488; project coordinator: Infineon Technologies; www.e-brains.org
4. P. Ramm, J.-Q. Lu, M. M. V. Taklo: "Introduction to wafer bonding," Handbook of Wafer Bonding, Wiley-VCH, 2012 (ISBN: 978-3-527-32646-4).
5. M. M. V. Taklo, K. Schjolberg-Henriksen, N. Malik, H. R. Tofteberg, E. Poppe, D. O. Vella, J. Borg, A. Attard, Z. Hajdarevic, A. Klumpp, P. Ramm, "Low-temperature bonding technologies for MEMS and 3D-IC," 4th IEEE Inter. Workshop on Low Temperature Bonding for 3D Integration (LTB-3D), 2014, p. 34.
6. "MANpower – energy harvesting and storage for low-frequency vibrations," granted by the European Commission under grant agreement no. 604360; project coordinator: Tyndall; www.themanpowerproject.eu
Peter Ramm received his Masters in Physics and Dr. rer. nat. degrees from the U. of Regensbuurg and is Head of the Department of Heterogeneous Integration at the Fraunhofer Research Institution for Modular Solid State Technologies (EMFT) and responsible for the core competence "Silicon Processes, Device and 3D Integration;" email Peter.Ramm@emft.fraunhofer.de
Peter Schneider received his Masters and PhD degrees in Electrical Engineering from the Dresden U. of Technology and is Director of the Design Automation Division, Fraunhofer Institute for Integrated Circuits, IIS-EAS.
Renzo Dal Molin received his Masters degree in Electronics and Biomedical Engineering from ESSTIN and the U. of Nancy France and is Director of Scientific and Technical Coordination for SORIN CRM, a business unit of SORIN GROUP.