Copper Pillar Flip Chip Momentum is Accelerating

By Lee Smith, VP Marketing & Business Development; Amkor Technology, Inc.

"The industry is moving rapidly to adopt copper pillar. We see this as a more significant shift than the transition from evaporation to plated bumping due to the architecture advantages copper pillar enables through finer bump pitch capabilities," noted Jan Vardaman in explaining the copper pillar FC emphasis in TechSearch International's new flip chip and wafer level packaging market report.¹

High Volume Copper Pillar FC Applications

A review of applications that transitioned to copper pillar FC provides support for rapid adoption outlooks. The following summarizes three distinct high-volume applications which transitioned to copper pillar FC over the past five years.

Figure 1: Copper pillar flip chip in RF modules. Source: Amkor Technology

In the first half of 2005, wireless device suppliers adopted copper pillar (CuP) FC in RF power amplifier and front-end modules through package assembly suppliers (Figure 1). This adoption was driven by cost / performance benefits such as improved thermal performance and improved electrical stability leading to higher final test yields. Another driver was lower total cost of ownership (CoO) through elimination of through-GaAs vias, thin wafer processing and back side gold plating; reduced package size vs. previous wirebonded modules; and the use of molded underfill, which provided package size and assembly cost benefits vs. capillary underfill.

At ECTC in May 2006, Intel’s paper titled, “Copper Die Bumps (1st level interconnect) and Low-k Dielectrics in 65nm High-volume Manufacturing” reported the adoption of copper pillar bumps on silicon based CMOS devices (Figure 2) as follows: “The benefits of copper die-side bumps for flip chip applications are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics…have made integrating copper bumps challenging... For the 65nm node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead package-side bumps in high volume manufacturing.”² Intel further cited benefits of copper bumps including improved electromigration resistance and thermal conductivity, simplified underbump metallization and a reduction of critical bump dimensions enabling extension to higher I/O densities.

Figure 2: SEM cross section of a Cu die bump mated to eutectic SnPb solder.
Source: Intel, 2006 Electronic Components and Technology Conference

Teardown reports on Intel devices over the past few years have shown an evolution of the copper pillar bump and solder attach structure as well as copper pillar being applied to a broad range of Intel devices including PC chipsets, Atom CPUs and Core i5 32nm CPU/GPU multichip package structures. ^3,4

In July of 2010 Amkor and Texas Instruments generated strong interest when announcing that they delivered the industry’s first fine pitch copper pillar flip chip packages to the market.⁵ The benefits reported for fine-pitch flip chip with copper pillar bumps include:

• Low cost
• Lead free
• Available with and without wafer re-passivation
• Fine-pitch flip chip on laminate package down to 5μm in line and 40/80μm staggered bump pitches
• Extends to finer pitch on silicon substrates for TSV and chip-to-chip FC stacking
• Superior electro-migration performance
• Fully developed finite element models for optimizing chip package interactions to improve long term reliability
• Qualified for advanced silicon node with low-k dielectrics

Figure 3: Fine pitch flip chip package on package structure and 50um in line copper pillar bump pitch cross section. Source: Amkor

Emerging Copper Pillar FC Technology

In October of 2010, Xilinx made a major announcement regarding the role stacked silicon interconnect technology will play in bringing their next generation field programmable gate array (FPGA) devices to market.⁶ Figure 4 illustrates Xilinx’s new FPGA package architecture with four 28nm die slices mounted to a silicon interposer through microbumps (which are based on Amkor copper pillar technology as reported by TechSearch in their new FC report). The Xilinx announcement included the following statements on bringing this technology to production: “Xilinx is well on the way to volume production of the first FPGAs with stacked silicon interconnect technology, having completed over five years of research and development with industry-leading suppliers and extensive testing on a series of multiple test vehicles. These test vehicles address process module development and integration, reliability assessment, supply-chain validation, design enablement, interposer known-good-die methodology, and microbump electromigration rules.”

Xilinx’s test vehicle-based reliability data reported includes:

• 1,000 cycles of package and wafer level Temperature Cycle B evaluation of TSV, C4 balls, and interposer microbump interconnects
• 1,000 hour high temperature storage evaluation of microbump joints
• 0.1% cumulative density function (CDF) for electromigration at the microbump joint

“Xilinx already has a robust supply chain in place for the technologies required to build the industry’s first FPGAs with stacked silicon interconnect technology. TSMC, Amkor and Ibiden contributed their combined resources and expertise for fabricating 28nm FPGAs and 65 nm silicon interposers, interconnect layers, microbumps, C4 balls and package substrates as well as performing wafer thinning, die separation, chip-on-chip attach, and package assembly.”

Xilinx’s web site also includes a report on “Technical Viability of Stacked Silicon Interconnect Technology”, which characterizes the microbumps as high-reliability.⁷

Figure 4: Xilinx new 3D package architecture with Si Interposer and microbumps

Copper Pillar Outlook

Through silicon via (TSV) technologies and 3D IC architectures have been a dominant theme in recent solid state and microelectronics conferences. This will continue in 2011 conferences and beyond. Technical papers on copper pillar flip chip have also been the rise and there are a few papers to note for 2011. At ECTC this June in Orlando, FL Texas Instruments and Amkor will present “Next Generation Fine Pitch Cu Pillar Technology – Enabling Next Generation Silicon Nodes”. Also Ahmer Syed of Amkor will present additional data beyond the data in Table 3 below on “Cu Pillar and µ-bump Electromigration Reliability Comparison with High Pb, SnPb, and SnAg Bumps.” ⁸

In the noted TechSearch’s 2010 flip chip and WLP market report, they forecast a 48% compound annual growth rate in copper pillar to nearly 6.5 million 300mm equivalent wafers demanded in 2014. This forecast provides strong support of Jan’s expectations for a rapid transition to copper pillar FC.

Table 3: Summary of failure data for different bump configurations. Source: Amkor Technologies

References:

1. E.J. Vardaman et al., “2010 Flip Chip and WLP: Market Projections and New Developments”, Dec. 2010
2. A. Yeoh et al., “Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing” 56th Electronic Components and Technology Conference, San Diego, CA, May 2006
3. Prismark Partners, Semiconductor and Packaging Report, Third Quarter Dec. 2008
4. Prismark Partners, Semiconductor and Packaging Report, First Quarter May 2010
5. July 7, 2010 Amkor press release, www.amkor.com / Investors: “Amkor Technology and Texas Instruments Deliver Industry's First Fine Pitch Copper Pillar Flip Chip Packages to Market” “New Packaging Platform Reduces Semiconductor Chip Size and Cost While Boosting Performance”
6. http://www.xilinx.com/technology/roadmap/ssi-technology.htm, Stacked Silicon Interconnect Technology White Paper, “Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency ”, WP380 (v1.0) October 27, 2010
7. http://www.xilinx.com/technology/roadmap/ssi-technology.htm, Technical Viability of Stacked Silicon Interconnect Technology by IBS Research, Oct. 2010 by Dr. Handel Jones, Founder and CEO, IBS Inc., October 2010
8. A. Syed, “Factors Affecting Electromigration and Current Carrying Capacity of FC and 3D IC Interconnects,” 12th Electronic Packaging and Technology Conference,  Singapore, Dec. 2010