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Advanced IC Packages Needed for Handheld Electronics
By Sandra Winkler [New Venture Research]
The demand for portable Internet connectivity devices such as cell phones, tablets, GPS devices, MP3 players, is very strong, in spite of poor economic times. What these items have in common is that they all pack an enormous amount of functionality into a very small space. To achieve this feat, these products must utilize more advanced packaging methods for the ICs inside the products, as it is the IC packages that hold the footprint to the PCB, thus determining the size of the PCB and, ultimately, the size of the final product. The chip packaging method also determines the speed and performance of that chip, as well as its battery consumption.
These devices are fueling demand for advanced IC packaging technologies such as system-in-package (SiP), stacked packages, fan-in QFNs, fan-out WLPs, interconnection styles of 3D and 2.5D through-silicon vias (TSVs), and flip chip.
Stacked Packages
Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are enjoying a high-demand market. Stacked package revenue will experience a 10%CAGR through 2015.
Through-Silicon Vias (TSVs)/3-D Interconnect
3D interconnection with TSVs creates a die stack with the shortest interconnection distance, enhancing the characteristics of high speed, low power consumption, reduced parasitics, and small form factor. This interconnection style utilizes vias that go through the silicon to electrically connect one die to the next in a vertical stack in place of wire bonds or other forms of connection.
In a world where small mobile devices connected to the Internet are in high demand, these are important features. By moving to 3D interconnection, the device can achieve 100 times the connectivity or bandwidth with less power consumption. With lines and traces on the silicon die moving to 45-, 32-, and 22-nm lithographies, utilizing TSVs is a way for the back-end interconnection to keep pace with the front-end manufacturing.
The notion of 2.5D was born in early 2010, as a variation of 3D integration. 3D integration stacks devices vertically using TSVs for electrical connection, and possibly an RDL (redistribution layer) created with a dielectric material as a layer to reroute the electrical connections between chips and allow the vias to travel to the lower substrate.
2.5D replaces the RDL with a silicon (or glass) interposer as the routing layer, so that the vias run through the interposer or substrate rather than through the active die. This interposer can be used to fan out or reroute the electrical traces of a device while routing the traces to another vehicle in a vertical dimension, such as the package substrate. These layers utilize microbumps on the interface to electrically connect to the next layer in the stack. Silicon interposers accommodate the CTE mismatch between the layers in a stack, acting as a stress reducer, thus improving reliability.
The identified potential markets for TSVs will climb from 35B units in 2010 to over 54 billion in 2015.
System in Package (SiP)
SiPs are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the number of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs. Revenue for SiPs will expand at a 5.4 percent CAGR through 2015.
Fan-In QFNs
To increase the reach of the QFN package involves extending the number of rows of leads from the usual one to two or three rows of leads. The leadframe is stamped or etched as in any other leadframe solution, but the leads are of various lengths, either two or three different lengths. When bent downward for connection to the PCB by trim and form equipment, the result is a multi-row, array-patterned package solution, know as a fan-in QFN. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. This includes extending its reach to higher bit MCUs and both logic and analog communications chips, largely bound for RF handheld gadgets that require a small-form-factor package. Though the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1%through 2015.
Fan-Out WLPs
Reconfigured or fan-out wafer-level packages (WLPs) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board. Fan-Out WLPs have a CAGR of 15.9% for revenue through 2015.
Advanced IC Packages
All these packages are advanced forms of IC packages, which add performance and/or reduced form factor to the mix. These attributes make them suitable for the handheld electronic gadgets that are currently in great demand.
Cellular handsets are the primary handheld electronic gadget that everyone wants to own. Their use is spreading around the world, especially in territories too vast to support wired communication lines. Cellular handsets are growing at an 8.5% CAGR between 2011 and 2015, and the smart phone subset of this market is growing at a 15.2% CAGR. These rates are far greater than for the economy as a whole.
More information can be found on these topics and others in the new report, Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition, from New Venture Research (newventureresearch.com).
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