Bits from BiTS Workshop 2012
BiTS Workshop 2012 got underway Sunday, March 4, 2012 with tutorials, tech talk, and an evening of market reports over dinner. John Diller, of IDI, talked about the geography of socket suppliers vs. their customers. First he differentiated between characterization sockets, which are used in development wherever engineers are doing development work. This is different than sockets used for burn-in and final test, which are used at manufacturing sites. He said suppliers tend to cluster where the selection happens, rather than where they are being used in manufacturing, oftentimes in detriment of support. He said suppliers must be truly global to be effective. "You can't be a small company based where sockets are being used, and not have a presence where selection is being made." He noted.
Jim Brandes of Multitest gave a brief presentation on what he calls 'specsmanship", to make the point that comparing contactors can be challenging, and that we're not always comparing apples to apples because of different specifications. This needs to change, he said, making a case for standardization. As an example, he talked about conductance, and how it is measured using different techniques by different manufacturers. Additionally, he addressed inductance specifications, and made a case for loop inductance vs. self inductance, saying that loop inductance is important for characterizing power delivery. Ultimately, he said specs are critical, but must be read with a grain of salt. "We need to be able to compare apples to apples, but don't want to end up with a lemon." He quipped.
Fred Taber, director of the BiTS Workshop, rounded out the evening with his annual socket market report. From 2009-2010, he reported 16% growth in the market. Substantial growth (42%) is projected for 2010-2015. Breaking it down to three socket categories, Taber noted a dramatic decline in price for production sockets over the last 10 years. 400-600 pin sockets priced at $9.00 in 1990 cost as little as $.01. Burn-in sockets are priced from $12-40, are ordered in large quantities, and have a per-pin production cost as low as $.02/pin. Finally, pricing for test socket is pin-count dependent. $1000 pin sockets can be priced as high as $10K.
The event got into full swing on Monday, and in addition to many technology sessions devoted to advancements in burn-in and test strategies, the day's program featured a number of keynote and distinguished speakers who offered BiTS attendees insight on the industry as a whole.
Jim Feldhan, president of Phoenix-based Semico Research, gave a brief forecast of the semiconductor market, and then focused his talk on 3D opportunities in the semiconductor industry. The worldwide GPD is on the road to recovery, with a projected 4.2% growth driven largely by emerging markets, improved U.S. and European economies, and sustained growth in China and India. Specifically to the semiconductor industry, Feldhan predicts an optimistic 10% growth in revenue in 2012. End products will continue to have richer semiconductor content such as more memory, radio, MEMS, applications and baseband processors. This is good news for 3D, because many of these functions will require the higher performance at lower power offered by 3D packaging.
"3D is sexy, but it's still going through puberty. We expect the technology to be adopted faster than it is," noted Feldhan, adding that for 5 years we've been hearing that 3D will be adopted in two years. He says the hold-up is largely due to gating issues such as the ecosystem, EDA tools, assembly and test processes, and product life and reliability testing. Up until 2012, there have been reliable and low cost solutions in traditional single die packages, and system-in-package with stacked die. However, the performance improvements from 2.5D interposer and 3D TSV devices will make them vital to memory in 2012 and memory + logic in 2014. According to Feldhan, 2012 will see pilot production for 3D DRAM with high volume manufacturing (HVM) coming in 2013. The hybrid memory cube (HMC) of DRAM on logic will be in pilot production in 2013, with HVM in 2014. 3D NAND will also be in pilot production in 2013 and HVM in 2014. From an applications perspective, the first to adopt 3D will likely be data centers and base stations, where the 10x performance at lower power consumption benefits offsets the cost of implementation. Consumer products will follow along as cost-of-ownership comes down. Challenges that 3D adoption will bring to the burn-in and test community will involve convincing OEMs to switch architecture and board designs. "Reliability is key. Life test and reliability testing is needed to prove to engineers that it's not a risky decision to switch the architecture." Said Feldhan, explaining that engineers tend to be risk averse, so there will need to be good documentation, extensive life and reliability test to explain away risk.
Package Level Test Challenges
Distinguished speakers, John Morrissey and Mark Hopman, of Intel, teamed up to discuss the evolution of test tooling strategy as it moves from being a commodity to an integral business enabler. They talked about both the technical and economic inference behind Moore's Law, which ultimately translates to more functionality in smaller devices at lower asking selling prices (ASP). Therefore future growth markets require a lower cost structure. These requirements pose a significant challenge to the test tooling community as a non-value add is to increase test complexity without adding cost to the end device. Ultimately, according to Morrissey and Hopman, tooling has not kept pace with the semiconductor industry. "Sockets are not able to meet dimensional needs," noted Hopman. "Suppliers want to help, but they have no idea what we do with that socket in the manufacturing environment." They called for more collaboration with suppliers and integrated design and usage teams. Rather than a horizontal approach, they are proposing a vertical approach. "Design and usage have to meet up together," said Morrissey. "Either its tight collaboration or some other way to reach vertical integration." The unspoken message to attendees: if suppliers can't meet Intel's needs, they'll take care of it in-house.
Networking opportunities are a vital part of every BiTS Workshop and this year was no different. The evening reception in the BiTS Expo gave attendees to experience both gastronomic and technology excellence. BiTS organizers pulled out all the stops this year with Tuesday's Bayou Bash, with Cajun cuisine and New Orleans jazz. One thing is for sure, it's going to be one to top in 2013.