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Exploring New Approaches to 3D Integration
By Andrew Smith, Ron Csermak, and Mark Vandermeulen ON Semiconductor
Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures. A robust, innovative approach, suitable for supporting low- to medium-volume applications while avoiding the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques, has been developed. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well suited for designs incorporating multiple ICs from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time-to-market.
Evolution of Device Packaging
Packaging technologies - from single-chip SMT packages to chip-on-board multi-chip modules (MCM) and package-on-package (POP) solutions - have continuously evolved to meet the ever-increasing demand for increased functionality at reduced size. 3D integration of vertically stacked ICs connected using TSV technology represents perhaps the ultimate evolution, however this technology is still several years away from full commercial adoption. Only a handful of suppliers and applications are in volume production, and issues of cost, thermal management, and development infrastructure remain before widespread acceptance of the technology.
Alternative Approaches to 3D Integration
An alternative approach to 3D integration involves bare die stacking using interposers (with or without integrated passive devices) and vertical interconnect structures to offer high levels of integration without the need for TSV technology. In this methodology, more traditional processes and assembly techniques are employed in novel ways using a SiP-based approach, providing a highly robust solution suitable for low- and medium-volume applications. By leveraging advances in fine-pitch flip chip, wafer thinning, and high-density thick film ceramic substrates, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar devices, co-packaged with discrete and/or integrated passive components. It circumvents the barriers to entry that OEMs face from alternative multi-chip packaging techniques, such as TSV. The approach is also independent of specific foundry processes and is therefore well suited for designs incorporating multiple ICs from different semiconductor manufacturing sources.
Figure 1: Comparison of TSV and SiP-based Integration approaches
Figure 2 below illustrates a conceptual chip stack using multiple ICs, vertically mounted using high density interposer and vertical interconnect (VI) structures. This flexible approach allows for co-packaging of multiple identical or dissimilar die alongside discrete and/or integrated passive devices in a highly scalable architecture. Ceramic VI structures utilized in the package provide both mechanical support for the stack and electrical connectivity between layers within the stack, and are easily customized to the pin count and geometry requirements of the application. The use of ceramic VI structures also allows for elimination of wirebonds, providing size and potential performance (electrical and thermal) improvements in the system.
Figure 2: Example of a multi-chip stack assembly
Case study: High thermal-load die stack
Figure 3 below illustrates one application of ceramic-based 3D stacking, in this case for a high density multi-chip memory stack.High thermal conductivity of the package is required to manage the thermal load of the component devices, and is achieved in part utilizing high thermal conductivity aluminum nitride (AlN) ceramic substrates and conductive epoxy.
Figure 3: High thermal load AlN SiP module
Case study: Miniaturized wireless audio DSP/transceiver module
Another example of how this approach can be applied in practice is illustrated below. Figure 4 outlines the functional block diagram for a wireless DSP/transceiver module used in hearing aids (in this case, the ON Semiconductor AYRETM audio digital signal processor). The system incorporates a variety of active and passive components which, due to the stringent size constraints of the end application, must be packaged in the smallest possible form factor. Technologies including high-density thick-film ceramic substrates and vertical interconnect structures, wafer/die thinning, fine-pitch flip chip assembly, and 3D stacking are all combined to yield the compact SiP assembly shown in Figure 5.
Figure 4: Block diagram of wireless hearing aid processor
Figure 5: Final assembly
Additional size reduction gains can be achieved by integrating passive devices into package substrates or interposers. Figure 6 shows an example of two active ICs assembled with VI structures, but in this case the top ceramic submodule is replaced by a silicon integrated capacitor array (ON Semiconductor SiPArray™ technology), eliminating the need for discrete capacitors and serving as a mounting / thin-film routing plane for the active device to which it is flip-chip mounted. This makes the assembly even thinner as the discretes are effectively "buried" into the substrate.
Figure 6: Chip stack with integrated passives
Summary
As the industry migrates to TSV-based 3D integration techniques, alternative 3D technologies based upon vertical die stacking are available now which offer high packing densities without TSV. These SiP-based chip stacking technologies offer lower development costs, supply chain stability, cross-foundry compatibility and more rapid time to market, providing new options for designers looking to miniaturize their assemblies.
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