LEDs a la EVG

While the LED market is growing, experts say that there needs to be a significant manufacturing cost reduction before LEDs will truly be a high volume product. The LED fabrication roadmap targets packaged LED prices of $2.20/klm by 2015. Silicon wafer level packaging is a key technology for packaging-cost reduction of HB-LEDs, enabling solid state lighting for general illumination. Equipment manufacturer, EV Group is making progress in this area, offering a suite of tools for all aspects of the LED manufacturing process. Chip Scale Review talked to EV Group's Dr, Thomas Uhrmann, Business Development Manager, about processes involved in wafer level packaging (WLP) for HB LEDS, and where EVG fits into the picture.

CSR: What is the current state of the HB LED market, and what needs to happen to facilitate high volume manufacturing (HVM)?

Uhrmann: There's an interesting phenomena going on with HB LEDS. Due to improved efficiency of LEDs, fewer units are required to achieve the same performance. For example, display backlighting used to require light bars around the perimeter of the screen, now only one at the bottom is needed. This has caused some overcapacity for the back-lighting market. Fortunately, general lighting offers a huge growth opportunity for LEDs. We're about 3-5 years off from LEDS being adopted for mass market lighting applications. However, there needs to be approximately a 10X reduction in manufacturing cost before HVM will be achieved.

CSR: What is the main motivation for WLP for HB LEDS?

Uhrmann: There are a number of technology and cost benefits to going with silicon WLP for HB LEDS. First is improved performance. The combination of a silicon substrate and metallic through silicon vias (TSVs) results in high thermal conductivity, which allows for effectively conducting heat from the LED die, enabling higher power operation and increased lifetime. There is a low coefficient of thermal expansion (CTE) between the silicon substrate and the sapphire LED chips, allowing highly reliable packaging even with the high thermal stress LEDs introduce to packages. Silicon anisotropic etching provides a cavity for highly reflective mirror coating. It also allows for wafer level integration of the IC circuitry and wafer level optics capability. Essentially, the WLP benefits can be summed up to include lower cost, smaller form factor, high reliability, and improved performance.

CSR: Can you describe the process flow for HB LEDS using WLP as opposed to traditional leadframe packaging?

Uhrmann: The first four WLP steps for manufacturing HB LEDS are similar to front-end processes for IC fabrication and include Zener diode fabrication, via etch, first metal deposition, plating, and CMP, followed by topside metallization and bumping. WLP processes begin with temporary bond of a silicon carrier wafer, wafer thinning, backside metallization and bumping, debonding, LED die attach, phosphor coating, lens molding and singulation (Figure 1)

Figure 1: WLP process flow for HB LEDs

EVG has introduced some cost effective processes into this process flow. For example, in order to create white light, the blue light emitted by the LEDs is partly converted by yellow broad-band phosphor to result in white light. EVG developed a phosphor spray coating process to conformally coat the LED dies that are populated on the Si wafer or directly on the LED wafer. Conformal phosphor coating is essential to get a consistent color of emitted light. Many of the other techniques like dispensing don't feature this and therefore the emitted color is not uniform across the array.

CSR: You mentioned four different chip designs for GaN-based LEDs in your presentation. What is the most advantageous and which WLP processes are most suited to accommodating it?

Uhrmann: The four primary chip designs are lateral, vertical thin film, thin film, and thin film flip chip. Lateral design is still the most common design in the industry. However the other chip designs offer better features such as the ability to deposit the mirror layer on the top side, and also bond the LED wafer to the carrier with higher heat conduction and / or good electrical performance. Processes to accommodate thin film designs include etch, pattern lithography, spray coating, thin wafer handling, temporary bonding and debonding, and advanced chip to wafer bonding, and nanoimprint lithography for wafer level optics, all of which fall into EVG's capabilities.

CSR: You talked about the benefits of NIL versus stepper lithography. Can you explain that?

Uhrmann: Well, nanoimprint lithography holds major benefits for two emerging technologies in LED manufacturing. First of all, patterned sapphire is often used to enhance the growth of the GaN layers as well as improve the extraction efficiency from the LEDs active layers. Reduced feature sizes result in increased throughput for etching the sapphire structure and overgrowth. Nanoimprint lithography is a very cost-efficient technology to produce these nanostructures, especially when considering the price advantage over lithography steppers. Secondly, photonic crystals are still under research at all major LED companies. These nanostructures need to be patterned after the LED is grown where substrates are highly warped. Lithography steppers face high difficulties to cope with the warpage, which is absolutely no problem for our newly developed Soft Molecular Scale Nanoimprint Lithography (SMS-NIL) technology.

CSR: As you already mentioned, EVG has solutions available for each step in the WLP process for LEDS. Could you elaborate on those?

Uhrmann: In order to improve costs and processes across the manufacturing flow, it's critical to make improvements at each stage. EVG offers tools that address steps from manufacturing LEDS themselves - such as for engineered substrates, LED processing using optical lithography and wafer bonding, technologies for enhanced light extraction - through to the packaging. For manufacturing structured silicon WLP, our longstanding experience in MEMS and WLP for ICs brings a big benefit to our customers because we are able to offer lithography solutions and process support. Another increasingly important process is the molding of secondary optics to control the emission pattern of the packaged LEDs. EVG is knowledgeable in this area, due to our position as a market and technology leader for CMOS image sensor packaging and wafer level optics. Our core competency is in the wafer bonding space, and includes permanent bonding as well as thin wafer handling solutions, temporary bonding and debonding. Ultimately, EVG's goal is to enable drastically reduced cost of ownership to propel LED manufacturing into high volume production, where the improvement of yield is becoming a more and more important.