Technology Considerations for Cost Effective HBLED Manufacturing

By Manish Ranjan, Ultratech Inc.

Over the last several years, we have witnessed a steady increase in the adoption of high-brightness, light-emitting diodes (HBLED) chips for several end market applications. While demand was initially driven by display chips, the pull for using HBLED chips for solid-state lighting applications is on the rise. It is anticipated that solid-state lighting will play a significant role in realizing global energy cost savings within the next several years. However, manufacturing cost reductions are critical to ensure wide spread adoption of solid-state lighting. These manufacturing cost reductions are typically achieved via wafer size transitions, improved tool productivity and process yield improvements. This article discusses some of the lithography challenges for achieving cost-effective manufacturing.

Figure 1 shows the expected LED growth in various end markets. Continued cost reductions will enable sustained adoption of these chips in key growth areas such as solid-state lighting markets (Figure 1). Lithography is one of the key process steps affecting the final device and yield performance for high-brightness LED manufacturing. In general there are six lithography steps in a conventional LED manufacturing process utilized for display manufacturing. Additional lithography layers may be added as companies transition to a vertical chip structure for solid-state lighting.

Figure 1: Expected LED growth in various end markets.

Many HB LED manufacturers that have historically utilized contact or proximity printers on 2" and 4" sapphire wafers are now transitioning to projection lithography. The use of projection lithography improves overlay, enables printing of much smaller minimum feature sizes without introducing defects, and provides superior resist profiles for improved line width control.¹ The effect of these process improvements is higher yield, which plays a critical role in lowering device manufacturing costs.

Technology Considerations

Some of the unique process challenges associated with fabrication of leading-edge HBLED chips include:

• Patterned Sapphire Substrates (PSS): Several HBLED chip manufacturers have adopted patterned sapphire substrates to increase light extraction efficiency. The PSS structure consists of a repeating grid structure that is etched into the sapphire to scatter light. The efficiency of the PSS increases as the size of the grid structure is reduced to finer features. In addition to enhancing light extraction efficiency, PSS structures also help reduce the dislocation defect density, which helps improve overall device efficiency. In general contact, proximity or projection aligners are not able to meet the resolution requirements for this exposure step. Most customers have transitioned to the use of stepper technology for this photolithography process sequence.

  1X stepper technology provides large depth of focus for this process step, which turn minimizes rework and provides robust operational performance during the photo process. Furthermore, it is possible for a stepper to compensate for topology variations across warped wafer substrates. This compensation can be accomplished by first mapping out the warpage profile of the wafer and then by adjusting the wafer tilt across the exposure steps. As warpage increases with larger wafer sizes, the ability of the lithography tool to compensate for substrate warpage becomes even more critical. Figure 2 shows the results of PSS exposure step.

  
  
  
  
• Metal Pad Exposure: Another challenging exposure step is the current spreading layer that is used to enhance the brightness of the LED chip. The current spreading features have small widths to maximize the current injection area across the device while minimizing the area of the LED that is blocked by the current spreading structures. Hence, transition to smaller finger width also enables increased current extraction efficiency.

There are a number of unique process considerations that must be addressed for this exposure step in addition to warped wafer processing capability. One such consideration is the use of rough epitaxial layers by certain customers in the Asia Pacific region. A key requirement for improving LED efficiency is to minimize surface reflection of visible light. To minimize surface reflection, many HBLED manufacturers are implementing a sub wavelength substrate coating (SWC). This can be accomplished by etching or growing a spiked surface coating. It should be noted that the SWC layer makes it difficult to see this layer in visible light, making it difficult to capture alignment targets at this level. Therefore, for maximum operational flexibility it is important to have a secondary off-axis alignment system which is capable of viewing these targets.

Economic Considerations:

To address the needs of cost-effective manufacturing, several companies are now utilizing 1X stepper technology for additional HBLED lithography layers. This adoption has been driven by the realization that their unique imaging requirements are subject to the same production necessities as semiconductor fabrication. The transition to stepper technology has been accelerated due to advantages with yield savings, recurring mask savings, imaging performance and superior process control.

Summary

The move towards clean renewable energy sources along with broad government incentives is driving the adoption of LED technology for the general lighting market segment. Significant improvements in manufacturing processes and infrastructure development are critical to ensure overall adoption of LED. Lithography is one of the critical processes affecting overall device yield and performance. The use of 1X steppers provides significantly superior technology and economic advantages for high-volume manufacturing environments.

References

1. D. Anberg, A. Hawryluk, "Low Cost of Ownership Lithography for High Brightness LED Manufacturing", LED Professional Review, Nov/Dec 2009