D43D: Designing for TSVS

By Francoise von Trapp, Sr. Technical Editor

Even if the workshop's formal title is Design for 3D (D43D), this year's agenda was clearly about designing for through silicon via (TSV) technologies. But rather than a technology process approach, the presentations focused on the design aspects of TSV, discussing not only the challenges being posed, but the areas where TSVs can ease the pain of current outdated technologies. A combined effort of Leti and Ecole Polytechnique Federale Lausanne, the event took place June 28 and 29, 2011 in at the Minatec Campus.

According to program organizer, Ahmed Jerraya, Leti, it's important for there to be collaboration between the design and process departments in order to bring technologies to market more quickly "3D is a success in Leti because design and technology people are working together. That way, process people are focusing on best options, and design people are understanding processes earlier, thereby working with better design rules," explained Jerraya. Since last year's event, Jerraya says there is now a better understanding of the 3D roadmap. "Today we know that in 2 years we will have 2.5 D done and how it will look. We know the next step will be a 3D active interposer. What we are going to have next year is 2.5 D in production. Last year we didn't know that." he said.

Improving Yield with Redundant TSVs

Some of the more compelling presentations during D43D were those that pointed the various ways TSVs can be of use beyond mere interconnects for 3D chip stacking. Youn-Long Lin, of National Tsing Hua University explained how designing in redundant TSVs can improve yields. During fabrication and bonding processes, some TSVs may fail so recovery mechanisms become necessary. However, doubling the number of TSVs would be too expensive to do. You have to weigh the trade-off between overhead cost and recovery rate expected from a scheme. One recommendation is a TSV chain scheme in which layers 1 and 2 are connected by 3 ordinary TSVs and one redundant TSV. However, this scheme assumes that the maximum number of TSVs in a layer is two, and can improve overall yield by 99.98%. The weakness in this scheme is that only one failure can be repaired. For cases with a large number of TSVs and a high failure rate, a TSV chain isn't suitable. In that case, Lin proposes a redundant TSV architecture that can improve yield with low overhead, using low cost processes. Rather than a chain, the scheme is a TSV grid, with some TSVs used for redundancy. A 5-1 ratio makes for a four-way shift and 5 possible sources of signal repair by detouring signals one by one. This grid scheme has a higher TSV redundancy utilization and routing flexibility.

Thermal Management with TSVs

According to Sachin Sapatnekar, from the University of Minnesota, thermal issues are amplified in 3D stacks because there is a heat-generating core in each layer with only one heat sink creating a thermal bottleneck. Additionally, he said TSVs cause stress because of the uneven coefficient of thermal expansion (CTE) between silicon and TSV material. This can result in mechanical failure of TSVs and changes in circuit behavior. However, according to Hu Xu of the Ecole Polytechnique Federale Lausanne, thermal TSVs can be used to significantly reduce the temperature of 3D circuits, but to accomplish this efficiently, an accurate heat transfer model for thermal TSVs are is required.

Less is More

Another interesting concept for TSV designers to consider is a less is more approach. According to Frederic Petrot, TIMA, that while TSV is certainly the most promising technology for vertical integration today, it may not be an overall panacea because where there are TSVs, there aren't transistors. The more TSVs there are, the less active area there is in a chip. He suggests using asynchronous TSVs in what he calls "network on a chip" that makes use of vertical serial links. He demonstrated a study of serialization that shows serialization can greatly improve overall area cost of vertical communication when using medium density TSVs. A 2x2x2 mesh including this design is currently being taped-out.

3D TSV technologies business expectations and outlooks

The day wrapped up with a 3D panel organized by Yann Guillou of ST Ericsson. The panel included Jacky Seiller, Amkor; Mickael Rien, ARM; Jason Phua, Global Foundries; Herb Reiter, eda2asic Consulting & Global Semiconductor Association; and Christophe Zinck, Yole. Yann opened the discussion saying that although we all "love TSV", No economy is working for the beauty of the technology only. So what is the benefit to a company to use this technology? According to Zinck, wide I/O DRAM on logic will be introduced in the 2014-15 time frame, and will drive the production of 3D IC. He noted that IDMS, MEMS foundries packaging houses and OSATs are all poised to take on more value, but at the same time investment and learning is required for all players. That said, Zinck also predicts that Samsung will probably come out with something sooner than 2015 because they have all the capabilities as an IDM, they have knowledge in TSV, and they are agnostic. "If they need to use memory from Elpida, they'll use memory from elpida." he said. Some key points from the discussion overal: virtually all flip chip products will migrate to a TSV based solution over the next 3-5 years, with or without interposer. TSVs are the fastest growing R&D segment of the electronics packaging industry with widest applications. Standards are needed to a certain extent or equipment costs will go through the roof. But as Reiter stated, we don't have to standardize everything and can differentiate in hardware and software. "Let's not burden ourselves with extra costs by differentiating where it doesn't make sense." he said. As Reiter so succinctly put it, we're dealing with a complex environment and it will take time. But leaders really have no choice but to invest because the reality is, 90% of the semiconductor companies can't fund 14 or 16nm node scaling. At the end of the day, we need to enable 3D technology.