Experts Address 3D TSVs at CEA-Leti

By Francoise von Trapp, Sr. Technical Editor

Support for industrialization of through silicon via processes (TSVs) is building at CEA-Leti in Grenoble. In fact, in his opening address at the research institute's Annual Reviews, June 26&27 2011, Leti CEO, Laurent Malier, cited progress in the organization's 3D integration program as being one of the year's biggest milestones. In January, Leti opened its 300mm pilot line, and became the first to transfer image sensor technology to 300mm technology.

Maria-Noelle Semaria, deputy director in charge of advanced research, Leti, talked about 3D TSVs in the frame of Leti's 'three pillar' approach to industrialization that includes a research platform, industrial pilot line, and manufacturing that allows for building strong foundations and leveraging knowhow. The first demonstration of via middle processes and Cu pillar bumping, Inauguration of the 3D 300mm line, and pre-announcement of Leti's Open 3D initiative adhere to these 3 pillars. Open 3D makes it possible to do proof of concept and small volume production for prototyping for industrial customers and universities by giving them access to 3D mature technologies at both 200 and 300mm.

Building on Semaria's comments, Mark Scannell also reported on Leti's 3D integration highlights of the past 12 months that includes not only the opening of the 300mm pilot line, but the first TSV produced there. Leti has broadened its horizons into Japan, entering into several 3D focused multiyear common labs with both Shinko and SPTS. Scannell talked about how Xilinx really opened the world's eyes to the idea of using TSVs in passive interposers as the first step to 3D TSVs. He pointed out that it's not necessary today to put TSVs in CMOS. We can still make a lot of improvements by putting TSVs in passive chips, such as increasing count and decreasing pitch of I/Os. Interposers enable the connection of fine pitch IC I/Os to low pitch I/Os of a substrate. He sees the ultimate evolution moving from 2D SOC, to 2.5D SOC, to 3D SOC; or silicon motherboard (Figure 1). For a short while 2.5 D will postpone the introduction of 3D because it meets requirements, noted Scannell, but ultimately 3D and 2.5 D will coexist as technologies while also existing as separate technologies.

Figure 1: Schematics of 2D, 2.5D and 3D system on chip (SOC) proposed by Leti.

Scannell also addressed remaining challenges to 3D TSVs from Leti's perspective, and offered some solutions. He sees design as an application-specific task. Leti offers process technology and has design rules for those technologies. Design itself generally comes from the partners, and is done quite manually at the moment. With regards to where middle of the line processes will take place, he says the space has yet to be identified, so why not do it in Europe? There's a packaging house located in Portugal (Nanium) that would be an option. Finally, when it comes to the die-to-wafer (D2W) vs. wafer-to-wafer (W2W) debate, Scannell sees D2W placement as a solution, but not for high accuracy, high-volume placement of chips in 3D stacks. The future will be about W2W stacking.

Speaking on behalf of IBM on the topic of packaging and 3D integration was David Danovitch, Sr. engineer in microelectronics packaging systems and technology. For quite some time, IBM has taken a position in support of 3D integration as a solution to traditional scaling, and Danovitch re-iterated this. He said as Moore's law meets diminishing returns, interconnects are playing a more important role with regard to performance. TSVs address the need for high bandwidth, low latency memory, and the need for higher I/O density. He also suggests using silicon in "and intelligent fashion" getting the best out of a chip through fab optimization, and integrating large amounts of low latency, high bandwidth memory. It's also important to remember that whether you're talking about 2D, 2.5D or 3D, you still need to connect to a carrier or board. As an example, one structural schematic IBM is partnering with SEMATECH on is heterogeneous Integration of RF and 45nm digital CMOS. To reduce noise across the chips, they've developed a 3D decoupling strata that integrates a TSV interposer between the processor and the laminate.

Danovitch says it's important to maintain a balance when integrating TSVs. Connecting to "fat" wires results in less integration density, whereas going thinner brings concerns of size mismatch and effects of internal stress, especially with copper filled TSVs. It's critical to balance integration in the copper micro-structure to optimize reliability during cycling, thereby minimizing proximity effects.

Ultimately, says Danovitch, the semiconductor industry will continue to respond to the ever increasing challenge of traditional scaling, but by itself will be insufficient to meet performance growth. Therefore, microelectronic packaging development and evolution can no longer be disregarded, but rather must be developed in a vertically integrated fashion that considers everything from transistor to TSV to final assembly.